-
- switch (getValueType(I->getType())) {
- default:
- std::cerr << "ERROR in LowerArgs: unknown type "
- << getValueType(I->getType()) << "\n";
- abort();
- case MVT::f32:
- // fixme? (well, will need to for weird FP structy stuff,
- // see intel ABI docs)
- case MVT::f64:
-//XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
- MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
- // floating point args go into f8..f15 as-needed, the increment
- argVreg[count] = // is below..:
- MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
- // FP args go into f8..f15 as needed: (hence the ++)
- argPreg[count] = args_FP[used_FPArgs++];
- argOpc[count] = IA64::FMOV;
- argt = newroot = DAG.getCopyFromReg(argVreg[count],
- getValueType(I->getType()), DAG.getRoot());
- break;
- case MVT::i1: // NOTE: as far as C abi stuff goes,
- // bools are just boring old ints
- case MVT::i8:
- case MVT::i16:
- case MVT::i32:
- case MVT::i64:
-//XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
- MF.addLiveIn(args_int[count]); // mark this register as liveIn
- argVreg[count] =
- MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
- argPreg[count] = args_int[count];
- argOpc[count] = IA64::MOV;
- argt = newroot =
- DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
- if ( getValueType(I->getType()) != MVT::i64)
- argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
- newroot);
- break;
- }
+
+ switch (getValueType(I->getType())) {
+ default:
+ std::cerr << "ERROR in LowerArgs: unknown type "
+ << getValueType(I->getType()) << "\n";
+ abort();
+ case MVT::f32:
+ // fixme? (well, will need to for weird FP structy stuff,
+ // see intel ABI docs)
+ case MVT::f64:
+//XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
+ MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
+ // floating point args go into f8..f15 as-needed, the increment
+ argVreg[count] = // is below..:
+ MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
+ // FP args go into f8..f15 as needed: (hence the ++)
+ argPreg[count] = args_FP[used_FPArgs++];
+ argOpc[count] = IA64::FMOV;
+ argt = newroot = DAG.getCopyFromReg(argVreg[count],
+ getValueType(I->getType()), DAG.getRoot());
+ break;
+ case MVT::i1: // NOTE: as far as C abi stuff goes,
+ // bools are just boring old ints
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ case MVT::i64:
+//XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
+ MF.addLiveIn(args_int[count]); // mark this register as liveIn
+ argVreg[count] =
+ MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
+ argPreg[count] = args_int[count];
+ argOpc[count] = IA64::MOV;
+ argt = newroot =
+ DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
+ if ( getValueType(I->getType()) != MVT::i64)
+ argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
+ newroot);
+ break;
+ }
- // Create the frame index object for this incoming parameter...
- ArgOffset = 16 + 8 * (count - 8);
- int FI = MFI->CreateFixedObject(8, ArgOffset);
-
- // Create the SelectionDAG nodes corresponding to a load
- //from this parameter
- SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
- argt = newroot = DAG.getLoad(getValueType(I->getType()),
- DAG.getEntryNode(), FIN);
+ // Create the frame index object for this incoming parameter...
+ ArgOffset = 16 + 8 * (count - 8);
+ int FI = MFI->CreateFixedObject(8, ArgOffset);
+
+ // Create the SelectionDAG nodes corresponding to a load
+ //from this parameter
+ SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
+ argt = newroot = DAG.getLoad(getValueType(I->getType()),
+ DAG.getEntryNode(), FIN);
- //promote to 64-bits, sign/zero extending based on type
- //of the argument
- if(Args[i].second->isSigned())
- Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64,
- Args[i].first);
- else
- Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64,
- Args[i].first);
- break;
+ //promote to 64-bits, sign/zero extending based on type
+ //of the argument
+ if(Args[i].second->isSigned())
+ Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64,
+ Args[i].first);
+ else
+ Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64,
+ Args[i].first);
+ break;
- // the constant:
- if(cast<ConstantSDNode>(N)->getValue()) // true:
- BuildMI(BB, IA64::CMPEQ, 2, Result)
- .addReg(IA64::r0).addReg(IA64::r0);
- else // false:
- BuildMI(BB, IA64::CMPNE, 2, Result)
- .addReg(IA64::r0).addReg(IA64::r0);
- return Result; // early exit
- }
+ // the constant:
+ if(cast<ConstantSDNode>(N)->getValue()) // true:
+ BuildMI(BB, IA64::CMPEQ, 2, Result).addReg(IA64::r0).addReg(IA64::r0);
+ else // false:
+ BuildMI(BB, IA64::CMPNE, 2, Result).addReg(IA64::r0).addReg(IA64::r0);
+ return Result; // early exit
+ }
- unsigned dummy = MakeReg(MVT::i64);
- // first load zero:
- BuildMI(BB, IA64::MOV, 1, dummy).addReg(IA64::r0);
- // ...then conditionally (PR:Tmp1) add 1:
- BuildMI(BB, IA64::TPCADDIMM22, 2, Result).addReg(dummy)
- .addImm(1).addReg(Tmp1);
- return Result; // XXX early exit!
- }
+ unsigned dummy = MakeReg(MVT::i64);
+ // first load zero:
+ BuildMI(BB, IA64::MOV, 1, dummy).addReg(IA64::r0);
+ // ...then conditionally (PR:Tmp1) add 1:
+ BuildMI(BB, IA64::TPCADDIMM22, 2, Result).addReg(dummy)
+ .addImm(1).addReg(Tmp1);
+ return Result; // XXX early exit!
+ }
- (CSD->getValue() >= 1) && (CSD->getValue() <= 4) ) { // we can:
-
- // ++FusedSHLADD; // Statistic
- Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
- int shl_amt = CSD->getValue();
- Tmp3 = SelectExpr(N.getOperand(1));
-
- BuildMI(BB, IA64::SHLADD, 3, Result)
- .addReg(Tmp1).addImm(shl_amt).addReg(Tmp3);
- return Result; // early exit
+ (CSD->getValue() >= 1) && (CSD->getValue() <= 4) ) { // we can:
+
+ // ++FusedSHLADD; // Statistic
+ Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
+ int shl_amt = CSD->getValue();
+ Tmp3 = SelectExpr(N.getOperand(1));
+
+ BuildMI(BB, IA64::SHLADD, 3, Result)
+ .addReg(Tmp1).addImm(shl_amt).addReg(Tmp3);
+ return Result; // early exit
- case 1: // adding a constant that's 14 bits
- BuildMI(BB, IA64::ADDIMM14, 2, Result).addReg(Tmp1).addSImm(Tmp3);
- return Result; // early exit
- } // fallthrough and emit a reg+reg ADD:
- Tmp2 = SelectExpr(N.getOperand(1));
- BuildMI(BB, IA64::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ case 1: // adding a constant that's 14 bits
+ BuildMI(BB, IA64::ADDIMM14, 2, Result).addReg(Tmp1).addSImm(Tmp3);
+ return Result; // early exit
+ } // fallthrough and emit a reg+reg ADD:
+ Tmp2 = SelectExpr(N.getOperand(1));
+ BuildMI(BB, IA64::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
BuildMI(BB, IA64::SETFSIG, 1, TempFR1).addReg(Tmp1);
BuildMI(BB, IA64::SETFSIG, 1, TempFR2).addReg(Tmp2);
BuildMI(BB, IA64::XMAL, 1, TempFR3).addReg(TempFR1).addReg(TempFR2)
BuildMI(BB, IA64::SETFSIG, 1, TempFR1).addReg(Tmp1);
BuildMI(BB, IA64::SETFSIG, 1, TempFR2).addReg(Tmp2);
BuildMI(BB, IA64::XMAL, 1, TempFR3).addReg(TempFR1).addReg(TempFR2)
- case 1: // subtracting *from* an 8 bit constant:
- BuildMI(BB, IA64::SUBIMM8, 2, Result).addSImm(Tmp3).addReg(Tmp2);
- return Result; // early exit
- } // fallthrough and emit a reg+reg SUB:
- Tmp1 = SelectExpr(N.getOperand(0));
- BuildMI(BB, IA64::SUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ case 1: // subtracting *from* an 8 bit constant:
+ BuildMI(BB, IA64::SUBIMM8, 2, Result).addSImm(Tmp3).addReg(Tmp2);
+ return Result; // early exit
+ } // fallthrough and emit a reg+reg SUB:
+ Tmp1 = SelectExpr(N.getOperand(0));
+ BuildMI(BB, IA64::SUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
- switch (Tmp3) {
- case 8: // if AND 0x00000000000000FF, be quaint and use zxt1
- BuildMI(BB, IA64::ZXT1, 1, Result).addReg(Tmp1);
- break;
- case 16: // if AND 0x000000000000FFFF, be quaint and use zxt2
- BuildMI(BB, IA64::ZXT2, 1, Result).addReg(Tmp1);
- break;
- case 32: // if AND 0x00000000FFFFFFFF, be quaint and use zxt4
- BuildMI(BB, IA64::ZXT4, 1, Result).addReg(Tmp1);
- break;
- default: // otherwise, use dep.z to paste zeros
- BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
- .addImm(0).addImm(Tmp3);
- break;
- }
- return Result; // early exit
+ switch (Tmp3) {
+ case 8: // if AND 0x00000000000000FF, be quaint and use zxt1
+ BuildMI(BB, IA64::ZXT1, 1, Result).addReg(Tmp1);
+ break;
+ case 16: // if AND 0x000000000000FFFF, be quaint and use zxt2
+ BuildMI(BB, IA64::ZXT2, 1, Result).addReg(Tmp1);
+ break;
+ case 32: // if AND 0x00000000FFFFFFFF, be quaint and use zxt4
+ BuildMI(BB, IA64::ZXT4, 1, Result).addReg(Tmp1);
+ break;
+ default: // otherwise, use dep.z to paste zeros
+ BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
+ .addImm(0).addImm(Tmp3);
+ break;
+ }
+ return Result; // early exit
- case 1: // division by a constant that's a power of 2
- Tmp1 = SelectExpr(N.getOperand(0));
- if(isSigned) { // argument could be negative, so emit some code:
- unsigned divAmt=Tmp3;
- unsigned tempGR1=MakeReg(MVT::i64);
- unsigned tempGR2=MakeReg(MVT::i64);
- unsigned tempGR3=MakeReg(MVT::i64);
- BuildMI(BB, IA64::SHRS, 2, tempGR1)
- .addReg(Tmp1).addImm(divAmt-1);
- BuildMI(BB, IA64::EXTRU, 3, tempGR2)
- .addReg(tempGR1).addImm(64-divAmt).addImm(divAmt);
- BuildMI(BB, IA64::ADD, 2, tempGR3)
- .addReg(Tmp1).addReg(tempGR2);
- BuildMI(BB, IA64::SHRS, 2, Result)
- .addReg(tempGR3).addImm(divAmt);
- }
- else // unsigned div-by-power-of-2 becomes a simple shift right:
- BuildMI(BB, IA64::SHRU, 2, Result).addReg(Tmp1).addImm(Tmp3);
- return Result; // early exit
+ case 1: // division by a constant that's a power of 2
+ Tmp1 = SelectExpr(N.getOperand(0));
+ if(isSigned) { // argument could be negative, so emit some code:
+ unsigned divAmt=Tmp3;
+ unsigned tempGR1=MakeReg(MVT::i64);
+ unsigned tempGR2=MakeReg(MVT::i64);
+ unsigned tempGR3=MakeReg(MVT::i64);
+ BuildMI(BB, IA64::SHRS, 2, tempGR1)
+ .addReg(Tmp1).addImm(divAmt-1);
+ BuildMI(BB, IA64::EXTRU, 3, tempGR2)
+ .addReg(tempGR1).addImm(64-divAmt).addImm(divAmt);
+ BuildMI(BB, IA64::ADD, 2, tempGR3)
+ .addReg(Tmp1).addReg(tempGR2);
+ BuildMI(BB, IA64::SHRS, 2, Result)
+ .addReg(tempGR3).addImm(divAmt);
+ }
+ else // unsigned div-by-power-of-2 becomes a simple shift right:
+ BuildMI(BB, IA64::SHRU, 2, Result).addReg(Tmp1).addImm(Tmp3);
+ return Result; // early exit
- // answer = q * (-b) + a
- unsigned ModulusResult = MakeReg(MVT::f64);
- unsigned TmpF = MakeReg(MVT::f64);
- unsigned TmpI = MakeReg(MVT::i64);
-
- BuildMI(BB, IA64::SUB, 2, TmpI).addReg(IA64::r0).addReg(Tmp2);
- BuildMI(BB, IA64::SETFSIG, 1, TmpF).addReg(TmpI);
- BuildMI(BB, IA64::XMAL, 3, ModulusResult)
- .addReg(TmpF15).addReg(TmpF).addReg(TmpF1);
- BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(ModulusResult);
+ // answer = q * (-b) + a
+ unsigned ModulusResult = MakeReg(MVT::f64);
+ unsigned TmpF = MakeReg(MVT::f64);
+ unsigned TmpI = MakeReg(MVT::i64);
+
+ BuildMI(BB, IA64::SUB, 2, TmpI).addReg(IA64::r0).addReg(Tmp2);
+ BuildMI(BB, IA64::SETFSIG, 1, TmpF).addReg(TmpI);
+ BuildMI(BB, IA64::XMAL, 3, ModulusResult)
+ .addReg(TmpF15).addReg(TmpF).addReg(TmpF1);
+ BuildMI(BB, IA64::GETFSIG, 1, Result).addReg(ModulusResult);
- if(ConstantSDNode *CSDN =
- dyn_cast<ConstantSDNode>(N.getOperand(1))) {
- // if we are comparing against a constant zero
- if(CSDN->getValue()==0)
- Tmp2 = IA64::r0; // then we can just compare against r0
- else
- Tmp2 = SelectExpr(N.getOperand(1));
- } else // not comparing against a constant
- Tmp2 = SelectExpr(N.getOperand(1));
-
- switch (SetCC->getCondition()) {
- default: assert(0 && "Unknown integer comparison!");
- case ISD::SETEQ:
- BuildMI(BB, IA64::CMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETGT:
- BuildMI(BB, IA64::CMPGT, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETGE:
- BuildMI(BB, IA64::CMPGE, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETLT:
- BuildMI(BB, IA64::CMPLT, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETLE:
- BuildMI(BB, IA64::CMPLE, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETNE:
- BuildMI(BB, IA64::CMPNE, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETULT:
- BuildMI(BB, IA64::CMPLTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETUGT:
- BuildMI(BB, IA64::CMPGTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETULE:
- BuildMI(BB, IA64::CMPLEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETUGE:
- BuildMI(BB, IA64::CMPGEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- }
+ if(ConstantSDNode *CSDN =
+ dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+ // if we are comparing against a constant zero
+ if(CSDN->getValue()==0)
+ Tmp2 = IA64::r0; // then we can just compare against r0
+ else
+ Tmp2 = SelectExpr(N.getOperand(1));
+ } else // not comparing against a constant
+ Tmp2 = SelectExpr(N.getOperand(1));
+
+ switch (SetCC->getCondition()) {
+ default: assert(0 && "Unknown integer comparison!");
+ case ISD::SETEQ:
+ BuildMI(BB, IA64::CMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETGT:
+ BuildMI(BB, IA64::CMPGT, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETGE:
+ BuildMI(BB, IA64::CMPGE, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETLT:
+ BuildMI(BB, IA64::CMPLT, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETLE:
+ BuildMI(BB, IA64::CMPLE, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETNE:
+ BuildMI(BB, IA64::CMPNE, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETULT:
+ BuildMI(BB, IA64::CMPLTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETUGT:
+ BuildMI(BB, IA64::CMPGTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETULE:
+ BuildMI(BB, IA64::CMPLEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETUGE:
+ BuildMI(BB, IA64::CMPGEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ }
- assert(SetCC->getOperand(0).getValueType() != MVT::f32 &&
- "error: SETCC should have had incoming f32 promoted to f64!\n");
-
- if(ConstantFPSDNode *CFPSDN =
- dyn_cast<ConstantFPSDNode>(N.getOperand(1))) {
-
- // if we are comparing against a constant +0.0 or +1.0
- if(CFPSDN->isExactlyValue(+0.0))
- Tmp2 = IA64::F0; // then we can just compare against f0
- else if(CFPSDN->isExactlyValue(+1.0))
- Tmp2 = IA64::F1; // or f1
- else
- Tmp2 = SelectExpr(N.getOperand(1));
- } else // not comparing against a constant
- Tmp2 = SelectExpr(N.getOperand(1));
-
- switch (SetCC->getCondition()) {
- default: assert(0 && "Unknown FP comparison!");
- case ISD::SETEQ:
- BuildMI(BB, IA64::FCMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETGT:
- BuildMI(BB, IA64::FCMPGT, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETGE:
- BuildMI(BB, IA64::FCMPGE, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETLT:
- BuildMI(BB, IA64::FCMPLT, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETLE:
- BuildMI(BB, IA64::FCMPLE, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETNE:
- BuildMI(BB, IA64::FCMPNE, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETULT:
- BuildMI(BB, IA64::FCMPLTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETUGT:
- BuildMI(BB, IA64::FCMPGTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETULE:
- BuildMI(BB, IA64::FCMPLEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case ISD::SETUGE:
- BuildMI(BB, IA64::FCMPGEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- }
+ assert(SetCC->getOperand(0).getValueType() != MVT::f32 &&
+ "error: SETCC should have had incoming f32 promoted to f64!\n");
+
+ if(ConstantFPSDNode *CFPSDN =
+ dyn_cast<ConstantFPSDNode>(N.getOperand(1))) {
+
+ // if we are comparing against a constant +0.0 or +1.0
+ if(CFPSDN->isExactlyValue(+0.0))
+ Tmp2 = IA64::F0; // then we can just compare against f0
+ else if(CFPSDN->isExactlyValue(+1.0))
+ Tmp2 = IA64::F1; // or f1
+ else
+ Tmp2 = SelectExpr(N.getOperand(1));
+ } else // not comparing against a constant
+ Tmp2 = SelectExpr(N.getOperand(1));
+
+ switch (SetCC->getCondition()) {
+ default: assert(0 && "Unknown FP comparison!");
+ case ISD::SETEQ:
+ BuildMI(BB, IA64::FCMPEQ, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETGT:
+ BuildMI(BB, IA64::FCMPGT, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETGE:
+ BuildMI(BB, IA64::FCMPGE, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETLT:
+ BuildMI(BB, IA64::FCMPLT, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETLE:
+ BuildMI(BB, IA64::FCMPLE, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETNE:
+ BuildMI(BB, IA64::FCMPNE, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETULT:
+ BuildMI(BB, IA64::FCMPLTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETUGT:
+ BuildMI(BB, IA64::FCMPGTU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETULE:
+ BuildMI(BB, IA64::FCMPLEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ case ISD::SETUGE:
+ BuildMI(BB, IA64::FCMPGEU, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ break;
+ }
- default: assert(0 && "Cannot load this type!");
- case MVT::i1: Opc = IA64::LD1; isBool=true; break;
- // FIXME: for now, we treat bool loads the same as i8 loads */
- case MVT::i8: Opc = IA64::LD1; break;
- case MVT::i16: Opc = IA64::LD2; break;
- case MVT::i32: Opc = IA64::LD4; break;
- case MVT::i64: Opc = IA64::LD8; break;
-
- case MVT::f32: Opc = IA64::LDF4; break;
- case MVT::f64: Opc = IA64::LDF8; break;
+ default: assert(0 && "Cannot load this type!");
+ case MVT::i1: Opc = IA64::LD1; isBool=true; break;
+ // FIXME: for now, we treat bool loads the same as i8 loads */
+ case MVT::i8: Opc = IA64::LD1; break;
+ case MVT::i16: Opc = IA64::LD2; break;
+ case MVT::i32: Opc = IA64::LD4; break;
+ case MVT::i64: Opc = IA64::LD8; break;
+
+ case MVT::f32: Opc = IA64::LDF4; break;
+ case MVT::f64: Opc = IA64::LDF8; break;
- // into a predicate register
- assert(Opc==IA64::LD1 && "problem loading a bool");
- unsigned dummy3 = MakeReg(MVT::i64);
- BuildMI(BB, Opc, 1, dummy3).addReg(dummy2);
- // we compare to 0. true? 0. false? 1.
- BuildMI(BB, IA64::CMPNE, 2, Result).addReg(dummy3).addReg(IA64::r0);
+ // into a predicate register
+ assert(Opc==IA64::LD1 && "problem loading a bool");
+ unsigned dummy3 = MakeReg(MVT::i64);
+ BuildMI(BB, Opc, 1, dummy3).addReg(dummy2);
+ // we compare to 0. true? 0. false? 1.
+ BuildMI(BB, IA64::CMPNE, 2, Result).addReg(dummy3).addReg(IA64::r0);
- // into a predicate register
- assert(Opc==IA64::LD1 && "problem loading a bool");
- unsigned dummy3 = MakeReg(MVT::i64);
- BuildMI(BB, Opc, 1, dummy3).addReg(dummy);
- // we compare to 0. true? 0. false? 1.
- BuildMI(BB, IA64::CMPNE, 2, Result).addReg(dummy3).addReg(IA64::r0);
+ // into a predicate register
+ assert(Opc==IA64::LD1 && "problem loading a bool");
+ unsigned dummy3 = MakeReg(MVT::i64);
+ BuildMI(BB, Opc, 1, dummy3).addReg(dummy);
+ // we compare to 0. true? 0. false? 1.
+ BuildMI(BB, IA64::CMPNE, 2, Result).addReg(dummy3).addReg(IA64::r0);
- // into a predicate register
- assert(Opc==IA64::LD1 && "problem loading a bool");
- unsigned dummy3 = MakeReg(MVT::i64);
- BuildMI(BB, Opc, 1, dummy3).addReg(dummy);
- // we compare to 0. true? 0. false? 1.
- BuildMI(BB, IA64::CMPNE, 2, Result).addReg(dummy3).addReg(IA64::r0);
+ // into a predicate register
+ assert(Opc==IA64::LD1 && "problem loading a bool");
+ unsigned dummy3 = MakeReg(MVT::i64);
+ BuildMI(BB, Opc, 1, dummy3).addReg(dummy);
+ // we compare to 0. true? 0. false? 1.
+ BuildMI(BB, IA64::CMPNE, 2, Result).addReg(dummy3).addReg(IA64::r0);
- // into a predicate register
- assert(Opc==IA64::LD1 && "problem loading a bool");
- unsigned dummy = MakeReg(MVT::i64);
- BuildMI(BB, Opc, 1, dummy).addReg(Tmp2);
- // we compare to 0. true? 0. false? 1.
- BuildMI(BB, IA64::CMPNE, 2, Result).addReg(dummy).addReg(IA64::r0);
- }
+ // into a predicate register
+ assert(Opc==IA64::LD1 && "problem loading a bool");
+ unsigned dummy = MakeReg(MVT::i64);
+ BuildMI(BB, Opc, 1, dummy).addReg(Tmp2);
+ // we compare to 0. true? 0. false? 1.
+ BuildMI(BB, IA64::CMPNE, 2, Result).addReg(dummy).addReg(IA64::r0);
+ }
- unsigned intArgs[] = {IA64::out0, IA64::out1, IA64::out2, IA64::out3,
- IA64::out4, IA64::out5, IA64::out6, IA64::out7 };
- unsigned FPArgs[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
- IA64::F12, IA64::F13, IA64::F14, IA64::F15 };
-
- switch(N.getOperand(i+2).getValueType())
- {
- default: // XXX do we need to support MVT::i1 here?
- Node->dump();
- N.getOperand(i).Val->dump();
- std::cerr << "Type for " << i << " is: " <<
- N.getOperand(i+2).getValueType() << std::endl;
- assert(0 && "Unknown value type for call");
- case MVT::i64:
- BuildMI(BB, IA64::MOV, 1, intArgs[i]).addReg(argvregs[i]);
- break;
- case MVT::f64:
- BuildMI(BB, IA64::FMOV, 1, FPArgs[used_FPArgs++])
- .addReg(argvregs[i]);
- // FIXME: we don't need to do this _all_ the time:
- BuildMI(BB, IA64::GETFD, 1, intArgs[i]).addReg(argvregs[i]);
- break;
- }
+ unsigned intArgs[] = {IA64::out0, IA64::out1, IA64::out2, IA64::out3,
+ IA64::out4, IA64::out5, IA64::out6, IA64::out7 };
+ unsigned FPArgs[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
+ IA64::F12, IA64::F13, IA64::F14, IA64::F15 };
+
+ switch(N.getOperand(i+2).getValueType())
+ {
+ default: // XXX do we need to support MVT::i1 here?
+ Node->dump();
+ N.getOperand(i).Val->dump();
+ std::cerr << "Type for " << i << " is: " <<
+ N.getOperand(i+2).getValueType() << std::endl;
+ assert(0 && "Unknown value type for call");
+ case MVT::i64:
+ BuildMI(BB, IA64::MOV, 1, intArgs[i]).addReg(argvregs[i]);
+ break;
+ case MVT::f64:
+ BuildMI(BB, IA64::FMOV, 1, FPArgs[used_FPArgs++])
+ .addReg(argvregs[i]);
+ // FIXME: we don't need to do this _all_ the time:
+ BuildMI(BB, IA64::GETFD, 1, intArgs[i]).addReg(argvregs[i]);
+ break;
+ }
- switch (N.getOperand(1).getValueType()) {
- default: assert(0 && "Cannot store this type!");
- case MVT::i1: Opc = IA64::ST1; isBool=true; break;
- // FIXME?: for now, we treat bool loads the same as i8 stores */
- case MVT::i8: Opc = IA64::ST1; break;
- case MVT::i16: Opc = IA64::ST2; break;
- case MVT::i32: Opc = IA64::ST4; break;
- case MVT::i64: Opc = IA64::ST8; break;
-
- case MVT::f32: Opc = IA64::STF4; break;
- case MVT::f64: Opc = IA64::STF8; break;
- }
+ switch (N.getOperand(1).getValueType()) {
+ default: assert(0 && "Cannot store this type!");
+ case MVT::i1: Opc = IA64::ST1; isBool=true; break;
+ // FIXME?: for now, we treat bool loads the same as i8 stores */
+ case MVT::i8: Opc = IA64::ST1; break;
+ case MVT::i16: Opc = IA64::ST2; break;
+ case MVT::i32: Opc = IA64::ST4; break;
+ case MVT::i64: Opc = IA64::ST8; break;
+
+ case MVT::f32: Opc = IA64::STF4; break;
+ case MVT::f64: Opc = IA64::STF8; break;
+ }
- switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
- default: assert(0 && "unknown type in truncstore");
- case MVT::i1: Opc = IA64::ST1; isBool=true; break;
- //FIXME: DAG does not promote this load?
- case MVT::i8: Opc = IA64::ST1; break;
- case MVT::i16: Opc = IA64::ST2; break;
- case MVT::i32: Opc = IA64::ST4; break;
- case MVT::f32: Opc = IA64::STF4; break;
- }
+ switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
+ default: assert(0 && "unknown type in truncstore");
+ case MVT::i1: Opc = IA64::ST1; isBool=true; break;
+ //FIXME: DAG does not promote this load?
+ case MVT::i8: Opc = IA64::ST1; break;
+ case MVT::i16: Opc = IA64::ST2; break;
+ case MVT::i32: Opc = IA64::ST4; break;
+ case MVT::f32: Opc = IA64::STF4; break;
+ }
- unsigned dummy = MakeReg(MVT::i64);
- unsigned dummy2 = MakeReg(MVT::i64);
- BuildMI(BB, IA64::ADD, 2, dummy)
- .addGlobalAddress(cast<GlobalAddressSDNode>
- (N.getOperand(2))->getGlobal()).addReg(IA64::r1);
- BuildMI(BB, IA64::LD8, 1, dummy2).addReg(dummy);
-
- if(!isBool)
- BuildMI(BB, Opc, 2).addReg(dummy2).addReg(Tmp1);
- else { // we are storing a bool, so emit a little pseudocode
- // to store a predicate register as one byte
- assert(Opc==IA64::ST1);
- unsigned dummy3 = MakeReg(MVT::i64);
- unsigned dummy4 = MakeReg(MVT::i64);
- BuildMI(BB, IA64::MOV, 1, dummy3).addReg(IA64::r0);
- BuildMI(BB, IA64::TPCADDIMM22, 2, dummy4)
- .addReg(dummy3).addImm(1).addReg(Tmp1); // if(Tmp1) dummy=0+1;
- BuildMI(BB, Opc, 2).addReg(dummy2).addReg(dummy4);
- }
+ unsigned dummy = MakeReg(MVT::i64);
+ unsigned dummy2 = MakeReg(MVT::i64);
+ BuildMI(BB, IA64::ADD, 2, dummy)
+ .addGlobalAddress(cast<GlobalAddressSDNode>
+ (N.getOperand(2))->getGlobal()).addReg(IA64::r1);
+ BuildMI(BB, IA64::LD8, 1, dummy2).addReg(dummy);
+
+ if(!isBool)
+ BuildMI(BB, Opc, 2).addReg(dummy2).addReg(Tmp1);
+ else { // we are storing a bool, so emit a little pseudocode
+ // to store a predicate register as one byte
+ assert(Opc==IA64::ST1);
+ unsigned dummy3 = MakeReg(MVT::i64);
+ unsigned dummy4 = MakeReg(MVT::i64);
+ BuildMI(BB, IA64::MOV, 1, dummy3).addReg(IA64::r0);
+ BuildMI(BB, IA64::TPCADDIMM22, 2, dummy4)
+ .addReg(dummy3).addImm(1).addReg(Tmp1); // if(Tmp1) dummy=0+1;
+ BuildMI(BB, Opc, 2).addReg(dummy2).addReg(dummy4);
+ }
- // FIXME? (what about bools?)
-
- unsigned dummy = MakeReg(MVT::i64);
- BuildMI(BB, IA64::MOV, 1, dummy)
- .addFrameIndex(cast<FrameIndexSDNode>(N.getOperand(2))->getIndex());
- BuildMI(BB, Opc, 2).addReg(dummy).addReg(Tmp1);
+ // FIXME? (what about bools?)
+
+ unsigned dummy = MakeReg(MVT::i64);
+ BuildMI(BB, IA64::MOV, 1, dummy)
+ .addFrameIndex(cast<FrameIndexSDNode>(N.getOperand(2))->getIndex());
+ BuildMI(BB, Opc, 2).addReg(dummy).addReg(Tmp1);
- Tmp2 = SelectExpr(N.getOperand(2)); //address
- if(!isBool)
- BuildMI(BB, Opc, 2).addReg(Tmp2).addReg(Tmp1);
- else { // we are storing a bool, so emit a little pseudocode
- // to store a predicate register as one byte
- assert(Opc==IA64::ST1);
- unsigned dummy3 = MakeReg(MVT::i64);
- unsigned dummy4 = MakeReg(MVT::i64);
- BuildMI(BB, IA64::MOV, 1, dummy3).addReg(IA64::r0);
- BuildMI(BB, IA64::TPCADDIMM22, 2, dummy4)
- .addReg(dummy3).addImm(1).addReg(Tmp1); // if(Tmp1) dummy=0+1;
- BuildMI(BB, Opc, 2).addReg(Tmp2).addReg(dummy4);
- }
+ Tmp2 = SelectExpr(N.getOperand(2)); //address
+ if(!isBool)
+ BuildMI(BB, Opc, 2).addReg(Tmp2).addReg(Tmp1);
+ else { // we are storing a bool, so emit a little pseudocode
+ // to store a predicate register as one byte
+ assert(Opc==IA64::ST1);
+ unsigned dummy3 = MakeReg(MVT::i64);
+ unsigned dummy4 = MakeReg(MVT::i64);
+ BuildMI(BB, IA64::MOV, 1, dummy3).addReg(IA64::r0);
+ BuildMI(BB, IA64::TPCADDIMM22, 2, dummy4)
+ .addReg(dummy3).addImm(1).addReg(Tmp1); // if(Tmp1) dummy=0+1;
+ BuildMI(BB, Opc, 2).addReg(Tmp2).addReg(dummy4);
+ }