14 files changed:
return get(RegNo).SuperRegs;
}
return get(RegNo).SuperRegs;
}
- /// getAsmName - Return the symbolic target-specific name for the
- /// specified physical register.
- const char *getAsmName(unsigned RegNo) const {
- return get(RegNo).AsmName;
- }
-
/// getName - Return the human-readable symbolic target-specific name for the
/// specified physical register.
const char *getName(unsigned RegNo) const {
/// getName - Return the human-readable symbolic target-specific name for the
/// specified physical register.
const char *getName(unsigned RegNo) const {
unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
O << '{'
unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
O << '{'
- << TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
+ << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
<< '}';
} else if (Modifier && strcmp(Modifier, "lane") == 0) {
unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 0 : 1,
&ARM::DPRRegClass);
<< '}';
} else if (Modifier && strcmp(Modifier, "lane") == 0) {
unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 0 : 1,
&ARM::DPRRegClass);
- O << TRI->getAsmName(DReg) << '[' << (RegNum & 1) << ']';
+ O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
- O << TRI->getAsmName(Reg);
+ O << getRegisterName(Reg);
}
} else
llvm_unreachable("not implemented");
}
} else
llvm_unreachable("not implemented");
const MachineOperand &MO2 = MI->getOperand(Op+1);
const MachineOperand &MO3 = MI->getOperand(Op+2);
const MachineOperand &MO2 = MI->getOperand(Op+1);
const MachineOperand &MO3 = MI->getOperand(Op+2);
- assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << TRI->getAsmName(MO1.getReg());
+ O << getRegisterName(MO1.getReg());
// Print the shift opc.
O << ", "
// Print the shift opc.
O << ", "
<< " ";
if (MO2.getReg()) {
<< " ";
if (MO2.getReg()) {
- assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
- O << TRI->getAsmName(MO2.getReg());
+ O << getRegisterName(MO2.getReg());
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
} else {
O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
} else {
O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
if (!MO2.getReg()) {
if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
if (!MO2.getReg()) {
if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
O << ", "
<< (char)ARM_AM::getAM2Op(MO3.getImm())
O << ", "
<< (char)ARM_AM::getAM2Op(MO3.getImm())
- << TRI->getAsmName(MO2.getReg());
+ << getRegisterName(MO2.getReg());
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
O << ", "
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
O << ", "
}
O << (char)ARM_AM::getAM2Op(MO2.getImm())
}
O << (char)ARM_AM::getAM2Op(MO2.getImm())
- << TRI->getAsmName(MO1.getReg());
+ << getRegisterName(MO1.getReg());
if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
O << ", "
if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
O << ", "
const MachineOperand &MO3 = MI->getOperand(Op+2);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
const MachineOperand &MO3 = MI->getOperand(Op+2);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
if (MO2.getReg()) {
O << ", "
<< (char)ARM_AM::getAM3Op(MO3.getImm())
if (MO2.getReg()) {
O << ", "
<< (char)ARM_AM::getAM3Op(MO3.getImm())
- << TRI->getAsmName(MO2.getReg())
+ << getRegisterName(MO2.getReg())
if (MO1.getReg()) {
O << (char)ARM_AM::getAM3Op(MO2.getImm())
if (MO1.getReg()) {
O << (char)ARM_AM::getAM3Op(MO2.getImm())
- << TRI->getAsmName(MO1.getReg());
+ << getRegisterName(MO1.getReg());
return;
} else if (Modifier && strcmp(Modifier, "base") == 0) {
// Used for FSTM{D|S} and LSTM{D|S} operations.
return;
} else if (Modifier && strcmp(Modifier, "base") == 0) {
// Used for FSTM{D|S} and LSTM{D|S} operations.
- O << TRI->getAsmName(MO1.getReg());
+ O << getRegisterName(MO1.getReg());
if (ARM_AM::getAM5WBFlag(MO2.getImm()))
O << "!";
return;
}
if (ARM_AM::getAM5WBFlag(MO2.getImm()))
O << "!";
return;
}
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
O << ", #"
if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
O << ", #"
const MachineOperand &MO3 = MI->getOperand(Op+2);
// FIXME: No support yet for specifying alignment.
const MachineOperand &MO3 = MI->getOperand(Op+2);
// FIXME: No support yet for specifying alignment.
- O << "[" << TRI->getAsmName(MO1.getReg()) << "]";
+ O << "[" << getRegisterName(MO1.getReg()) << "]";
if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
if (MO2.getReg() == 0)
O << "!";
else
if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
if (MO2.getReg() == 0)
O << "!";
else
- O << ", " << TRI->getAsmName(MO2.getReg());
+ O << ", " << getRegisterName(MO2.getReg());
const MachineOperand &MO1 = MI->getOperand(Op);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
const MachineOperand &MO1 = MI->getOperand(Op);
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
- O << "[pc, +" << TRI->getAsmName(MO1.getReg()) << "]";
+ O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
- O << "[" << TRI->getAsmName(MO1.getReg());
- O << ", " << TRI->getAsmName(MO2.getReg()) << "]";
+ O << "[" << getRegisterName(MO1.getReg());
+ O << ", " << getRegisterName(MO2.getReg()) << "]";
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
- O << ", " << TRI->getAsmName(MO3.getReg());
+ O << ", " << getRegisterName(MO3.getReg());
else if (unsigned ImmOffs = MO2.getImm()) {
O << ", #" << ImmOffs;
if (Scale > 1)
else if (unsigned ImmOffs = MO2.getImm()) {
O << ", #" << ImmOffs;
if (Scale > 1)
void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
const MachineOperand &MO1 = MI->getOperand(Op);
const MachineOperand &MO2 = MI->getOperand(Op+1);
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
if (unsigned ImmOffs = MO2.getImm())
O << ", #" << ImmOffs << " * 4";
O << "]";
if (unsigned ImmOffs = MO2.getImm())
O << ", #" << ImmOffs << " * 4";
O << "]";
unsigned Reg = MO1.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
unsigned Reg = MO1.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
- O << TRI->getAsmName(Reg);
+ O << getRegisterName(Reg);
// Print the shift opc.
O << ", "
// Print the shift opc.
O << ", "
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
unsigned OffImm = MO2.getImm();
if (OffImm) // Don't print +0.
unsigned OffImm = MO2.getImm();
if (OffImm) // Don't print +0.
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
int32_t OffImm = (int32_t)MO2.getImm();
// Don't print +0.
int32_t OffImm = (int32_t)MO2.getImm();
// Don't print +0.
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
const MachineOperand &MO1 = MI->getOperand(OpNum);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
int32_t OffImm = (int32_t)MO2.getImm() / 4;
// Don't print +0.
int32_t OffImm = (int32_t)MO2.getImm() / 4;
// Don't print +0.
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
const MachineOperand &MO3 = MI->getOperand(OpNum+2);
const MachineOperand &MO2 = MI->getOperand(OpNum+1);
const MachineOperand &MO3 = MI->getOperand(OpNum+2);
- O << "[" << TRI->getAsmName(MO1.getReg());
+ O << "[" << getRegisterName(MO1.getReg());
assert(MO2.getReg() && "Invalid so_reg load / store address!");
assert(MO2.getReg() && "Invalid so_reg load / store address!");
- O << ", " << TRI->getAsmName(MO2.getReg());
+ O << ", " << getRegisterName(MO2.getReg());
unsigned ShAmt = MO3.getImm();
if (ShAmt) {
unsigned ShAmt = MO3.getImm();
if (ShAmt) {
}
void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
}
void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
- O << "[pc, " << TRI->getAsmName(MI->getOperand(OpNum).getReg());
+ O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
if (MI->getOpcode() == ARM::t2TBH)
O << ", lsl #1";
O << ']';
if (MI->getOpcode() == ARM::t2TBH)
O << ", lsl #1";
O << ']';
default: return true; // Unknown modifier.
case 'a': // Print as a memory address.
if (MI->getOperand(OpNum).isReg()) {
default: return true; // Unknown modifier.
case 'a': // Print as a memory address.
if (MI->getOperand(OpNum).isReg()) {
- O << "[" << TRI->getAsmName(MI->getOperand(OpNum).getReg()) << "]";
+ O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
return false;
}
// Fallthrough
return false;
}
// Fallthrough
if (MO.getType() == MachineOperand::MO_Register) {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Not physreg??");
if (MO.getType() == MachineOperand::MO_Register) {
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Not physreg??");
- O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
+ O << getRegisterName(MO.getReg());
} else if (MO.isImm()) {
O << MO.getImm();
assert(MO.getImm() < (1 << 30));
} else if (MO.isImm()) {
O << MO.getImm();
assert(MO.getImm() < (1 << 30));
void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
- const TargetRegisterInfo &RI = *TM.getRegisterInfo();
-
switch (MO.getType()) {
case MachineOperand::MO_Register:
switch (MO.getType()) {
case MachineOperand::MO_Register:
- O << RI.get(MO.getReg()).AsmName;
+ O << getRegisterName(MO.getReg());
return;
case MachineOperand::MO_Immediate:
return;
case MachineOperand::MO_Immediate:
case MachineOperand::MO_Register:
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should be already mapped!");
case MachineOperand::MO_Register:
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should be already mapped!");
- O << RI.get(MO.getReg()).AsmName;
+ O << getRegisterName(MO.getReg());
break;
case MachineOperand::MO_Immediate:
break;
case MachineOperand::MO_Immediate:
unsigned RegNo = MO.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(RegNo) &&
"Not physreg??");
unsigned RegNo = MO.getReg();
assert(TargetRegisterInfo::isPhysicalRegister(RegNo) &&
"Not physreg??");
- O << TM.getRegisterInfo()->get(RegNo).AsmName;
+ O << getRegisterName(RegNo);
}
void printOperand(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.isReg()) {
}
void printOperand(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
if (MO.isReg()) {
- assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
- O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
+ O << getRegisterName(MO.getReg());
} else if (MO.isImm()) {
O << MO.getImm();
} else {
} else if (MO.isImm()) {
O << MO.getImm();
} else {
// the value contained in the register. For this reason, the darwin
// assembler requires that we print r0 as 0 (no r) when used as the base.
const MachineOperand &MO = MI->getOperand(OpNo);
// the value contained in the register. For this reason, the darwin
// assembler requires that we print r0 as 0 (no r) when used as the base.
const MachineOperand &MO = MI->getOperand(OpNo);
- O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
- O << ", ";
+ O << getRegisterName(MO.getReg()) << ", ";
printOperand(MI, OpNo+1);
}
printOperand(MI, OpNo+1);
}
const MachineOperand &MO = MI->getOperand(OpNum);
switch (MO.getType()) {
case MachineOperand::MO_Register:
const MachineOperand &MO = MI->getOperand(OpNum);
switch (MO.getType()) {
case MachineOperand::MO_Register:
- assert (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- "Virtual registers should be already mapped!");
- O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
+ O << getRegisterName(MO.getReg());
return;
case MachineOperand::MO_Immediate:
if (!Modifier || strcmp(Modifier, "nohash"))
return;
case MachineOperand::MO_Immediate:
if (!Modifier || strcmp(Modifier, "nohash"))
unsigned stackSize = MF.getFrameInfo()->getStackSize();
unsigned stackSize = MF.getFrameInfo()->getStackSize();
- O << "\t.frame\t" << '$' << LowercaseString(RI.get(stackReg).AsmName)
+ O << "\t.frame\t" << '$' << LowercaseString(getRegisterName(stackReg))
<< ',' << stackSize << ','
<< ',' << stackSize << ','
- << '$' << LowercaseString(RI.get(returnReg).AsmName)
+ << '$' << LowercaseString(getRegisterName(returnReg))
void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
const MachineOperand &MO = MI->getOperand(opNum);
void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
const MachineOperand &MO = MI->getOperand(opNum);
- const TargetRegisterInfo &RI = *TM.getRegisterInfo();
bool closeP = false;
if (MO.getTargetFlags())
bool closeP = false;
if (MO.getTargetFlags())
- switch (MO.getType())
- {
+ switch (MO.getType()) {
case MachineOperand::MO_Register:
case MachineOperand::MO_Register:
- if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
- O << '$' << LowercaseString (RI.get(MO.getReg()).AsmName);
- else
- O << '$' << MO.getReg();
+ O << '$' << LowercaseString(getRegisterName(MO.getReg()));
break;
case MachineOperand::MO_Immediate:
break;
case MachineOperand::MO_Immediate:
switch (MO.getType()) {
case MachineOperand::MO_Register:
switch (MO.getType()) {
case MachineOperand::MO_Register:
- if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
- O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
- else
- llvm_unreachable("not implemented");
+ O << getRegisterName(MO.getReg());
return;
case MachineOperand::MO_Immediate:
return;
case MachineOperand::MO_Immediate:
- const char *RegName = TM.getRegisterInfo()->get(RegNo).AsmName;
+ const char *RegName = getRegisterName(RegNo);
// Linux assembler (Others?) does not take register mnemonics.
// FIXME - What about special registers used in mfspr/mtspr?
if (!Subtarget.isDarwin()) RegName = stripRegisterPrefix(RegName);
// Linux assembler (Others?) does not take register mnemonics.
// FIXME - What about special registers used in mfspr/mtspr?
if (!Subtarget.isDarwin()) RegName = stripRegisterPrefix(RegName);
}
switch (MO.getType()) {
case MachineOperand::MO_Register:
}
switch (MO.getType()) {
case MachineOperand::MO_Register:
- if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
- O << "%" << LowercaseString (RI.get(MO.getReg()).AsmName);
- else
- O << "%reg" << MO.getReg();
+ O << "%" << LowercaseString(getRegisterName(MO.getReg()));
break;
case MachineOperand::MO_Immediate:
break;
case MachineOperand::MO_Immediate:
assert(0 && "Invalid subreg modifier");
}
assert(0 && "Invalid subreg modifier");
}
- O << '%' << TRI->getAsmName(Reg);
+ O << '%' << getRegisterName(Reg);
return;
}
case MachineOperand::MO_Immediate:
return;
}
case MachineOperand::MO_Immediate:
switch (MO.getType()) {
default: llvm_unreachable("unknown operand type!");
case MachineOperand::MO_Register: {
switch (MO.getType()) {
default: llvm_unreachable("unknown operand type!");
case MachineOperand::MO_Register: {
- assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
- "Virtual registers should not make it this far!");
O << '%';
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
O << '%';
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
Reg = getX86SubSuperRegister(Reg, VT);
}
- O << TRI->getAsmName(Reg);
+ O << X86ATTInstPrinter::getRegisterName(Reg);
- O << '%'<< TRI->getAsmName(Reg);
+ O << '%' << X86ATTInstPrinter::getRegisterName(Reg);
const char *Modifier) {
switch (MO.getType()) {
case MachineOperand::MO_Register: {
const char *Modifier) {
switch (MO.getType()) {
case MachineOperand::MO_Register: {
- assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()));
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
EVT VT = (strcmp(Modifier,"subreg64") == 0) ?
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
EVT VT = (strcmp(Modifier,"subreg64") == 0) ?
const MachineOperand &MO = MI->getOperand(opNum);
switch (MO.getType()) {
case MachineOperand::MO_Register:
const MachineOperand &MO = MI->getOperand(opNum);
switch (MO.getType()) {
case MachineOperand::MO_Register:
- O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
+ O << getRegisterName(MO.getReg());
break;
case MachineOperand::MO_Immediate:
O << MO.getImm();
break;
case MachineOperand::MO_Immediate:
O << MO.getImm();
// Check for mov mnemonic
unsigned src, dst, srcSR, dstSR;
if (TM.getInstrInfo()->isMoveInstr(*MI, src, dst, srcSR, dstSR)) {
// Check for mov mnemonic
unsigned src, dst, srcSR, dstSR;
if (TM.getInstrInfo()->isMoveInstr(*MI, src, dst, srcSR, dstSR)) {
- O << "\tmov ";
- O << TM.getRegisterInfo()->get(dst).AsmName;
- O << ", ";
- O << TM.getRegisterInfo()->get(src).AsmName;
- O << "\n";
+ O << "\tmov " << getRegisterName(dst) << ", ";
+ O << getRegisterName(src) << '\n';
return;
}
printInstruction(MI);
return;
}
printInstruction(MI);