git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171697
91177308-0d34-0410-b5e6-
96231b3b80d8
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
- def #NAME# : ALU32_rr<(outs IntRegs:$dst),
+ def NAME : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
") $dst = ")#mnemonic#"($src2, $src3)",
(ins PredRegs:$src1, IntRegs:$src2, IntRegs: $src3),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
") $dst = ")#mnemonic#"($src2, $src3)",
multiclass ALU32_Pred<string mnemonic, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass ALU32_Pred<string mnemonic, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- defm _c#NAME# : ALU32_Pbase<mnemonic, PredNot, 0>;
+ defm _c#NAME : ALU32_Pbase<mnemonic, PredNot, 0>;
- defm _cdn#NAME# : ALU32_Pbase<mnemonic, PredNot, 1>;
+ defm _cdn#NAME : ALU32_Pbase<mnemonic, PredNot, 1>;
multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
let isPredicable = 1 in
multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_rr in {
let isPredicable = 1 in
- def #NAME# : ALU32_rr<(outs IntRegs:$dst),
+ def NAME : ALU32_rr<(outs IntRegs:$dst),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = "#mnemonic#"($src1, $src2)",
[(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
(ins IntRegs:$src1, IntRegs:$src2),
"$dst = "#mnemonic#"($src1, $src2)",
[(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
//===----------------------------------------------------------------------===//
multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
//===----------------------------------------------------------------------===//
multiclass ALU32ri_Pbase<string mnemonic, bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
- def #NAME# : ALU32_ri<(outs IntRegs:$dst),
+ def NAME : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
") $dst = ")#mnemonic#"($src2, #$src3)",
(ins PredRegs:$src1, IntRegs:$src2, s8Ext: $src3),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew,".new) $dst = ",
") $dst = ")#mnemonic#"($src2, #$src3)",
multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass ALU32ri_Pred<string mnemonic, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- defm _c#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 0>;
+ defm _c#NAME : ALU32ri_Pbase<mnemonic, PredNot, 0>;
- defm _cdn#NAME# : ALU32ri_Pbase<mnemonic, PredNot, 1>;
+ defm _cdn#NAME : ALU32ri_Pbase<mnemonic, PredNot, 1>;
let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
isPredicable = 1 in
let CextOpcode = CextOp, BaseOpcode = CextOp#_ri in {
let opExtendable = 2, isExtentSigned = 1, opExtentBits = 16,
isPredicable = 1 in
- def #NAME# : ALU32_ri<(outs IntRegs:$dst),
+ def NAME : ALU32_ri<(outs IntRegs:$dst),
(ins IntRegs:$src1, s16Ext:$src2),
"$dst = "#mnemonic#"($src1, #$src2)",
[(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
(ins IntRegs:$src1, s16Ext:$src2),
"$dst = "#mnemonic#"($src1, #$src2)",
[(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$src1),
multiclass TFR_Pred<bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass TFR_Pred<bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- def _c#NAME# : ALU32_rr<(outs IntRegs:$dst),
- (ins PredRegs:$src1, IntRegs:$src2),
+ def _c#NAME : ALU32_rr<(outs IntRegs:$dst),
+ (ins PredRegs:$src1, IntRegs:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
[]>;
// Predicate new
let PNewValue = "new" in
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
[]>;
// Predicate new
let PNewValue = "new" in
- def _cdn#NAME# : ALU32_rr<(outs IntRegs:$dst),
- (ins PredRegs:$src1, IntRegs:$src2),
+ def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
+ (ins PredRegs:$src1, IntRegs:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
[]>;
}
!if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
[]>;
}
multiclass TFR_base<string CextOp> {
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let isPredicable = 1 in
multiclass TFR_base<string CextOp> {
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let isPredicable = 1 in
- def #NAME# : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
+ def NAME : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1),
multiclass TFR64_Pred<bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass TFR64_Pred<bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- def _c#NAME# : ALU32_rr<(outs DoubleRegs:$dst),
- (ins PredRegs:$src1, DoubleRegs:$src2),
+ def _c#NAME : ALU32_rr<(outs DoubleRegs:$dst),
+ (ins PredRegs:$src1, DoubleRegs:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
[]>;
// Predicate new
let PNewValue = "new" in
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = $src2",
[]>;
// Predicate new
let PNewValue = "new" in
- def _cdn#NAME# : ALU32_rr<(outs DoubleRegs:$dst),
- (ins PredRegs:$src1, DoubleRegs:$src2),
+ def _cdn#NAME : ALU32_rr<(outs DoubleRegs:$dst),
+ (ins PredRegs:$src1, DoubleRegs:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
[]>;
}
!if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = $src2",
[]>;
}
multiclass TFR64_base<string CextOp> {
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let isPredicable = 1 in
multiclass TFR64_base<string CextOp> {
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let isPredicable = 1 in
- def #NAME# : ALU32_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
+ def NAME : ALU32_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1),
multiclass TFRI_Pred<bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass TFRI_Pred<bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- def _c#NAME# : ALU32_ri<(outs IntRegs:$dst),
- (ins PredRegs:$src1, s12Ext:$src2),
+ def _c#NAME : ALU32_ri<(outs IntRegs:$dst),
+ (ins PredRegs:$src1, s12Ext:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
[]>;
// Predicate new
let PNewValue = "new" in
!if(PredNot, "if (!$src1", "if ($src1")#") $dst = #$src2",
[]>;
// Predicate new
let PNewValue = "new" in
- def _cdn#NAME# : ALU32_rr<(outs IntRegs:$dst),
- (ins PredRegs:$src1, s12Ext:$src2),
+ def _cdn#NAME : ALU32_rr<(outs IntRegs:$dst),
+ (ins PredRegs:$src1, s12Ext:$src2),
!if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
[]>;
}
!if(PredNot, "if (!$src1", "if ($src1")#".new) $dst = #$src2",
[]>;
}
let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
let opExtendable = 1, opExtentBits = 16, isMoveImm = 1, isPredicable = 1,
isReMaterializable = 1 in
let CextOpcode = CextOp, BaseOpcode = CextOp#I in {
let opExtendable = 1, opExtentBits = 16, isMoveImm = 1, isPredicable = 1,
isReMaterializable = 1 in
- def #NAME# : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
+ def NAME : ALU32_ri<(outs IntRegs:$dst), (ins s16Ext:$src1),
"$dst = #$src1",
[(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
"$dst = #$src1",
[(set (i32 IntRegs:$dst), s16ExtPred:$src1)]>;
multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,
bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
- def #NAME# : LDInst2<(outs RC:$dst),
+ def NAME : LDInst2<(outs RC:$dst),
(ins PredRegs:$src1, MEMri:$addr),
#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($addr)",
(ins PredRegs:$src1, MEMri:$addr),
#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($addr)",
multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass LD_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- defm _c#NAME# : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
+ defm _c#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
- defm _cdn#NAME# : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
+ defm _cdn#NAME : LD_MEMri_Pbase<mnemonic, RC, PredNot, 1>;
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
- def #NAME# : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
+ def NAME : LDInst2<(outs RC:$dst), (ins MEMri:$addr),
"$dst = "#mnemonic#"($addr)",
[]>;
"$dst = "#mnemonic#"($addr)",
[]>;
multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
multiclass LD_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
- def #NAME# : LDInst2<(outs RC:$dst),
- (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
+ def NAME : LDInst2<(outs RC:$dst),
+ (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3),
#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($src2+#$src3)",
[]>;
#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($src2+#$src3)",
[]>;
multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass LD_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- defm _c#NAME# : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
+ defm _c#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
- defm _cdn#NAME# : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
+ defm _cdn#NAME : LD_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 1>;
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1, AddedComplexity = 20 in
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
let opExtendable = 2, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1, AddedComplexity = 20 in
- def #NAME# : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
+ def NAME : LDInst2<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset),
"$dst = "#mnemonic#"($src1+#$offset)",
[]>;
"$dst = "#mnemonic#"($src1+#$offset)",
[]>;
multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
multiclass LD_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
- def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
+ def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
(ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($src2++#$offset)",
(ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset),
#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($src2++#$offset)",
multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
Operand ImmOp, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass LD_PostInc_Pred<string mnemonic, RegisterClass RC,
Operand ImmOp, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- defm _c#NAME# : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
+ defm _c#NAME : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
// Predicate new
let Predicates = [HasV4T], validSubTargets = HasV4SubT in
defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
// Predicate new
let Predicates = [HasV4T], validSubTargets = HasV4SubT in
defm _cdn#NAME#_V4 : LD_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
let BaseOpcode = "POST_"#BaseOp in {
let isPredicable = 1 in
let BaseOpcode = "POST_"#BaseOp in {
let isPredicable = 1 in
- def #NAME# : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
- (ins IntRegs:$src1, ImmOp:$offset),
+ def NAME : LDInst2PI<(outs RC:$dst, IntRegs:$dst2),
+ (ins IntRegs:$src1, ImmOp:$offset),
"$dst = "#mnemonic#"($src1++#$offset)",
[],
"$src1 = $dst2">;
"$dst = "#mnemonic#"($src1++#$offset)",
[],
"$src1 = $dst2">;
multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
multiclass ST_MEMri_Pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
- def #NAME# : STInst2<(outs),
+ def NAME : STInst2<(outs),
(ins PredRegs:$src1, MEMri:$addr, RC: $src2),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($addr) = $src2",
(ins PredRegs:$src1, MEMri:$addr, RC: $src2),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($addr) = $src2",
multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass ST_MEMri_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- defm _c#NAME# : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
+ defm _c#NAME : ST_MEMri_Pbase<mnemonic, RC, PredNot, 0>;
// Predicate new
let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
// Predicate new
let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
- def #NAME# : STInst2<(outs),
+ def NAME : STInst2<(outs),
(ins MEMri:$addr, RC:$src),
#mnemonic#"($addr) = $src",
[]>;
(ins MEMri:$addr, RC:$src),
#mnemonic#"($addr) = $src",
[]>;
multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
multiclass ST_Idxd_Pbase<string mnemonic, RegisterClass RC, Operand predImmOp,
bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
- def #NAME# : STInst2<(outs),
+ def NAME : STInst2<(outs),
(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($src2+#$src3) = $src4",
(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($src2+#$src3) = $src4",
multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
bit PredNot> {
let PredSense = #!if(PredNot, "false", "true"), isPredicated = 1 in {
multiclass ST_Idxd_Pred<string mnemonic, RegisterClass RC, Operand predImmOp,
bit PredNot> {
let PredSense = #!if(PredNot, "false", "true"), isPredicated = 1 in {
- defm _c#NAME# : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
+ defm _c#NAME : ST_Idxd_Pbase<mnemonic, RC, predImmOp, PredNot, 0>;
// Predicate new
let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
// Predicate new
let validSubTargets = HasV4SubT, Predicates = [HasV4T] in
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
- def #NAME# : STInst2<(outs),
+ def NAME : STInst2<(outs),
(ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
#mnemonic#"($src1+#$src2) = $src3",
[]>;
(ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
#mnemonic#"($src1+#$src2) = $src3",
[]>;
multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
multiclass ld_idxd_shl_pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
- def #NAME# : LDInst2<(outs RC:$dst),
+ def NAME : LDInst2<(outs RC:$dst),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#"$dst = "#mnemonic#"($src2+$src3<<#$offset)",
multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass ld_idxd_shl_pred<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- defm _c#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
+ defm _c#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 0>;
- defm _cdn#NAME# : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
+ defm _cdn#NAME : ld_idxd_shl_pbase<mnemonic, RC, PredNot, 1>;
multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
let isPredicable = 1 in
multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
let isPredicable = 1 in
- def #NAME#_V4 : LDInst2<(outs RC:$dst),
+ def NAME#_V4 : LDInst2<(outs RC:$dst),
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
"$dst = "#mnemonic#"($src1+$src2<<#$offset)",
[]>, Requires<[HasV4T]>;
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$offset),
"$dst = "#mnemonic#"($src1+$src2<<#$offset)",
[]>, Requires<[HasV4T]>;
multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
multiclass ST_Idxd_shl_Pbase<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
- def #NAME# : STInst2<(outs),
+ def NAME : STInst2<(outs),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
RC:$src5),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
RC:$src5),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass ST_Idxd_shl_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- defm _c#NAME# : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
+ defm _c#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 0>;
- defm _cdn#NAME# : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
+ defm _cdn#NAME : ST_Idxd_shl_Pbase<mnemonic, RC, PredNot, 1>;
multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
let isPredicable = 1 in
multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
let isPredicable = 1 in
- def #NAME#_V4 : STInst2<(outs),
+ def NAME#_V4 : STInst2<(outs),
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
#mnemonic#"($src1+$src2<<#$src3) = $src4",
[]>,
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
#mnemonic#"($src1+$src2<<#$src3) = $src4",
[]>,
multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
multiclass ST_Idxd_shl_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
- def #NAME#_nv_V4 : NVInst_V4<(outs),
+ def NAME#_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
RC:$src5),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$src4,
RC:$src5),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass ST_Idxd_shl_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- defm _c#NAME# : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
+ defm _c#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 0>;
- defm _cdn#NAME# : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
+ defm _cdn#NAME : ST_Idxd_shl_Pbase_nv<mnemonic, RC, PredNot, 1>;
multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
let isPredicable = 1 in
multiclass ST_Idxd_shl_nv<string mnemonic, string CextOp, RegisterClass RC> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
let isPredicable = 1 in
- def #NAME#_nv_V4 : NVInst_V4<(outs),
+ def NAME#_nv_V4 : NVInst_V4<(outs),
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
#mnemonic#"($src1+$src2<<#$src3) = $src4.new",
[]>,
(ins IntRegs:$src1, IntRegs:$src2, u2Imm:$src3, RC:$src4),
#mnemonic#"($src1+$src2<<#$src3) = $src4.new",
[]>,
multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
- def #NAME# : STInst2<(outs),
+ def NAME : STInst2<(outs),
(ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($src2+#$src3) = #$src4",
(ins PredRegs:$src1, IntRegs:$src2, OffsetOp:$src3, s6Ext:$src4),
#!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($src2+#$src3) = #$src4",
multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass ST_Imm_Pred<string mnemonic, Operand OffsetOp, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- defm _c#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
+ defm _c#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 0>;
- defm _cdn#NAME# : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
+ defm _cdn#NAME : ST_Imm_Pbase<mnemonic, OffsetOp, PredNot, 1>;
multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
- def #NAME#_V4 : STInst2<(outs),
+ def NAME#_V4 : STInst2<(outs),
(ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
#mnemonic#"($src1+#$src2) = #$src3",
[]>,
(ins IntRegs:$src1, OffsetOp:$src2, s8Ext:$src3),
#mnemonic#"($src1+#$src2) = #$src3",
[]>,
multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
Operand predImmOp, bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
multiclass ST_Idxd_Pbase_nv<string mnemonic, RegisterClass RC,
Operand predImmOp, bit isNot, bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
- def #NAME#_nv_V4 : NVInst_V4<(outs),
+ def NAME#_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($src2+#$src3) = $src4.new",
(ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC: $src4),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($src2+#$src3) = $src4.new",
multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass ST_Idxd_Pred_nv<string mnemonic, RegisterClass RC, Operand predImmOp,
bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- defm _c#NAME# : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
+ defm _c#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 0>;
- defm _cdn#NAME# : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
+ defm _cdn#NAME : ST_Idxd_Pbase_nv<mnemonic, RC, predImmOp, PredNot, 1>;
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in {
let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
- def #NAME#_nv_V4 : NVInst_V4<(outs),
+ def NAME#_nv_V4 : NVInst_V4<(outs),
(ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
#mnemonic#"($src1+#$src2) = $src3.new",
[]>,
(ins IntRegs:$src1, ImmOp:$src2, RC:$src3),
#mnemonic#"($src1+#$src2) = $src3.new",
[]>,
multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
multiclass ST_MEMri_Pbase_nv<string mnemonic, RegisterClass RC, bit isNot,
bit isPredNew> {
let PNewValue = #!if(isPredNew, "new", "") in
- def #NAME#_nv_V4 : NVInst_V4<(outs),
+ def NAME#_nv_V4 : NVInst_V4<(outs),
(ins PredRegs:$src1, MEMri:$addr, RC: $src2),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($addr) = $src2.new",
(ins PredRegs:$src1, MEMri:$addr, RC: $src2),
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
") ")#mnemonic#"($addr) = $src2.new",
multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
multiclass ST_MEMri_Pred_nv<string mnemonic, RegisterClass RC, bit PredNot> {
let PredSense = #!if(PredNot, "false", "true") in {
- defm _c#NAME# : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
+ defm _c#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 0>;
- defm _cdn#NAME# : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 1>;
+ defm _cdn#NAME : ST_MEMri_Pbase_nv<mnemonic, RC, PredNot, 1>;
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
let CextOpcode = CextOp, BaseOpcode = CextOp in {
let opExtendable = 1, isExtentSigned = 1, opExtentBits = ImmBits,
isPredicable = 1 in
- def #NAME#_nv_V4 : NVInst_V4<(outs),
+ def NAME#_nv_V4 : NVInst_V4<(outs),
(ins MEMri:$addr, RC:$src),
#mnemonic#"($addr) = $src.new",
[]>,
(ins MEMri:$addr, RC:$src),
#mnemonic#"($addr) = $src.new",
[]>,
let DecoderNamespace = "Mips64" in {
multiclass Atomic2Ops64<PatFrag Op> {
let DecoderNamespace = "Mips64" in {
multiclass Atomic2Ops64<PatFrag Op> {
- def #NAME# : Atomic2Ops<Op, CPU64Regs, CPURegs>,
- Requires<[NotN64, HasStdEnc]>;
- def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
- Requires<[IsN64, HasStdEnc]> {
+ def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>,
+ Requires<[NotN64, HasStdEnc]>;
+ def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
+ Requires<[IsN64, HasStdEnc]> {
let isCodeGenOnly = 1;
}
}
multiclass AtomicCmpSwap64<PatFrag Op> {
let isCodeGenOnly = 1;
}
}
multiclass AtomicCmpSwap64<PatFrag Op> {
- def #NAME# : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
- Requires<[NotN64, HasStdEnc]>;
- def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
- Requires<[IsN64, HasStdEnc]> {
+ def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
+ Requires<[NotN64, HasStdEnc]>;
+ def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
+ Requires<[IsN64, HasStdEnc]> {
let isCodeGenOnly = 1;
}
}
let isCodeGenOnly = 1;
}
}
multiclass LoadM<string opstr, RegisterClass RC,
SDPatternOperator OpNode = null_frag> {
multiclass LoadM<string opstr, RegisterClass RC,
SDPatternOperator OpNode = null_frag> {
- def #NAME# : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
- def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
+ def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
+ def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
multiclass StoreM<string opstr, RegisterClass RC,
SDPatternOperator OpNode = null_frag> {
multiclass StoreM<string opstr, RegisterClass RC,
SDPatternOperator OpNode = null_frag> {
- def #NAME# : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
- def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
+ def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
+ def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
}
multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
}
multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
- def #NAME# : LoadLeftRight<opstr, OpNode, RC, mem>,
- Requires<[NotN64, HasStdEnc]>;
- def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
- Requires<[IsN64, HasStdEnc]> {
+ def NAME : LoadLeftRight<opstr, OpNode, RC, mem>,
+ Requires<[NotN64, HasStdEnc]>;
+ def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
+ Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
}
multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
}
multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
- def #NAME# : StoreLeftRight<opstr, OpNode, RC, mem>,
- Requires<[NotN64, HasStdEnc]>;
- def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
- Requires<[IsN64, HasStdEnc]> {
+ def NAME : StoreLeftRight<opstr, OpNode, RC, mem>,
+ Requires<[NotN64, HasStdEnc]>;
+ def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
+ Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
[(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
multiclass Atomic2Ops32<PatFrag Op> {
[(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
multiclass Atomic2Ops32<PatFrag Op> {
- def #NAME# : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
- def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
- Requires<[IsN64, HasStdEnc]> {
+ def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
+ def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
+ Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
}
}
let DecoderNamespace = "Mips64";
}
}
[(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
multiclass AtomicCmpSwap32<PatFrag Op> {
[(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
multiclass AtomicCmpSwap32<PatFrag Op> {
- def #NAME# : AtomicCmpSwap<Op, CPURegs, CPURegs>,
- Requires<[NotN64, HasStdEnc]>;
- def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
- Requires<[IsN64, HasStdEnc]> {
+ def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>,
+ Requires<[NotN64, HasStdEnc]>;
+ def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
+ Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
}
}
let DecoderNamespace = "Mips64";
}
}