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Reduce t2 ldr/str instructions to the correct t1 versions when there's an
author
Jim Grosbach
<grosbach@apple.com>
Fri, 3 Dec 2010 19:47:11 +0000
(19:47 +0000)
committer
Jim Grosbach
<grosbach@apple.com>
Fri, 3 Dec 2010 19:47:11 +0000
(19:47 +0000)
immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120833
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM/Thumb2SizeReduction.cpp
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diff --git
a/lib/Target/ARM/Thumb2SizeReduction.cpp
b/lib/Target/ARM/Thumb2SizeReduction.cpp
index 950c95ab1cb91e743dc4a6802e2b4d1dcba60ebe..b0714988dde07bb1d6ac1e8b0c36a20c6d5fe642 100644
(file)
--- a/
lib/Target/ARM/Thumb2SizeReduction.cpp
+++ b/
lib/Target/ARM/Thumb2SizeReduction.cpp
@@
-106,19
+106,19
@@
namespace {
// FIXME: Clean this up after splitting each Thumb load / store opcode
// into multiple ones.
// FIXME: Clean this up after splitting each Thumb load / store opcode
// into multiple ones.
- { ARM::t2LDRi12,ARM::tLDR
,
ARM::tLDRspi, 5, 8, 1, 0, 0,0, 1 },
+ { ARM::t2LDRi12,ARM::tLDR
i,
ARM::tLDRspi, 5, 8, 1, 0, 0,0, 1 },
{ ARM::t2LDRs, ARM::tLDR, 0, 0, 0, 1, 0, 0,0, 1 },
{ ARM::t2LDRs, ARM::tLDR, 0, 0, 0, 1, 0, 0,0, 1 },
- { ARM::t2LDRBi12,ARM::tLDRB
,
0, 5, 0, 1, 0, 0,0, 1 },
+ { ARM::t2LDRBi12,ARM::tLDRB
i,
0, 5, 0, 1, 0, 0,0, 1 },
{ ARM::t2LDRBs, ARM::tLDRB, 0, 0, 0, 1, 0, 0,0, 1 },
{ ARM::t2LDRBs, ARM::tLDRB, 0, 0, 0, 1, 0, 0,0, 1 },
- { ARM::t2LDRHi12,ARM::tLDRH
,
0, 5, 0, 1, 0, 0,0, 1 },
+ { ARM::t2LDRHi12,ARM::tLDRH
i,
0, 5, 0, 1, 0, 0,0, 1 },
{ ARM::t2LDRHs, ARM::tLDRH, 0, 0, 0, 1, 0, 0,0, 1 },
{ ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 1 },
{ ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 1 },
{ ARM::t2LDRHs, ARM::tLDRH, 0, 0, 0, 1, 0, 0,0, 1 },
{ ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 1 },
{ ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 1 },
- { ARM::t2STRi12,ARM::tSTR
,
ARM::tSTRspi, 5, 8, 1, 0, 0,0, 1 },
+ { ARM::t2STRi12,ARM::tSTR
i,
ARM::tSTRspi, 5, 8, 1, 0, 0,0, 1 },
{ ARM::t2STRs, ARM::tSTR, 0, 0, 0, 1, 0, 0,0, 1 },
{ ARM::t2STRs, ARM::tSTR, 0, 0, 0, 1, 0, 0,0, 1 },
- { ARM::t2STRBi12,ARM::tSTRB
,
0, 5, 0, 1, 0, 0,0, 1 },
+ { ARM::t2STRBi12,ARM::tSTRB
i,
0, 5, 0, 1, 0, 0,0, 1 },
{ ARM::t2STRBs, ARM::tSTRB, 0, 0, 0, 1, 0, 0,0, 1 },
{ ARM::t2STRBs, ARM::tSTRB, 0, 0, 0, 1, 0, 0,0, 1 },
- { ARM::t2STRHi12,ARM::tSTRH
,
0, 5, 0, 1, 0, 0,0, 1 },
+ { ARM::t2STRHi12,ARM::tSTRH
i,
0, 5, 0, 1, 0, 0,0, 1 },
{ ARM::t2STRHs, ARM::tSTRH, 0, 0, 0, 1, 0, 0,0, 1 },
{ ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 1 },
{ ARM::t2STRHs, ARM::tSTRH, 0, 0, 0, 1, 0, 0,0, 1 },
{ ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 1 },