git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189430
91177308-0d34-0410-b5e6-
96231b3b80d8
class AFPR64<bits<16> Enc, string n, list<Register> subregs>
: MipsRegWithSubRegs<Enc, n, subregs> {
let SubRegIndices = [sub_lo, sub_hi];
class AFPR64<bits<16> Enc, string n, list<Register> subregs>
: MipsRegWithSubRegs<Enc, n, subregs> {
let SubRegIndices = [sub_lo, sub_hi];
+ let CoveredBySubRegs = 1;
}
// Mips 128-bit (aliased) MSA Registers
}
// Mips 128-bit (aliased) MSA Registers
// * FGR32 - 32 32-bit registers (single float only mode)
def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
// * FGR32 - 32 32-bit registers (single float only mode)
def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
-def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>;
+def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
+ Unallocatable;
def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
// Return Values and Arguments
def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
// Return Values and Arguments