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clk: rockchip: rk3399: remove re-enable pmucru clk_gate/pclk_alive
author
Xing Zheng
<zhengxing@rock-chips.com>
Mon, 28 Mar 2016 02:39:12 +0000
(10:39 +0800)
committer
Xing Zheng
<zhengxing@rock-chips.com>
Mon, 28 Mar 2016 02:44:03 +0000
(10:44 +0800)
These are not gating default when the SoC startup, so we don't need
to re-enable them.
Change-Id: I956a31345fe7f24b973db6c9e49d87a2988ac7d6
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
drivers/clk/rockchip/clk-rk3399.c
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diff --git
a/drivers/clk/rockchip/clk-rk3399.c
b/drivers/clk/rockchip/clk-rk3399.c
index bd84ef15097fa8dd82d0c25e05be241c45fdf1d3..639eaf608dbd3e1fd1b2dfa72423669602fea6bb 100644
(file)
--- a/
drivers/clk/rockchip/clk-rk3399.c
+++ b/
drivers/clk/rockchip/clk-rk3399.c
@@
-21,12
+21,6
@@
#include <dt-bindings/clock/rk3399-cru.h>
#include "clk.h"
#include <dt-bindings/clock/rk3399-cru.h>
#include "clk.h"
-#define RK3399_PMUGRF_SOC_CON0 0x180
-#define RK3399_PMUCRU_PCLK_GATE_MASK 0x1
-#define RK3399_PMUCRU_PCLK_GATE_SHIFT 4
-#define RK3399_PMUCRU_PCLK_ALIVE_MASK 0x1
-#define RK3399_PMUCRU_PCLK_ALIVE_SHIFT 6
-
enum rk3399_plls {
lpll, bpll, dpll, cpll, gpll, npll, vpll,
};
enum rk3399_plls {
lpll, bpll, dpll, cpll, gpll, npll, vpll,
};
@@
-1503,7
+1497,6
@@
static void __init rk3399_pmu_clk_init(struct device_node *np)
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
- struct regmap *grf;
reg_base = of_iomap(np, 0);
if (!reg_base) {
reg_base = of_iomap(np, 0);
if (!reg_base) {
@@
-1517,22
+1510,6
@@
static void __init rk3399_pmu_clk_init(struct device_node *np)
return;
}
return;
}
- grf = rockchip_clk_get_grf(ctx);
- if (IS_ERR(grf)) {
- pr_err("%s: pmugrf regmap not available\n", __func__);
- return;
- }
-
- /* enable gate for pclk_pmu_src */
- regmap_write(grf, RK3399_PMUGRF_SOC_CON0,
- HIWORD_UPDATE(0, RK3399_PMUCRU_PCLK_GATE_MASK,
- RK3399_PMUCRU_PCLK_GATE_SHIFT));
-
- /* enable pclk_alive_gpll_src gate */
- regmap_write(grf, RK3399_PMUGRF_SOC_CON0,
- HIWORD_UPDATE(0, RK3399_PMUCRU_PCLK_ALIVE_MASK,
- RK3399_PMUCRU_PCLK_ALIVE_SHIFT));
-
rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
ARRAY_SIZE(rk3399_pmu_pll_clks), -1);