+
+
+#if 0 //3288
+#define SET_RGMII { \
+ grf_writel(GMAC_PHY_INTF_SEL_RGMII, RK3288_GRF_SOC_CON1); \
+ grf_writel(GMAC_RMII_MODE_CLR, RK3288_GRF_SOC_CON1); \
+ grf_writel(GMAC_RXCLK_DLY_ENABLE, RK3288_GRF_SOC_CON3); \
+ grf_writel(GMAC_TXCLK_DLY_ENABLE, RK3288_GRF_SOC_CON3); \
+ grf_writel(GMAC_CLK_RX_DL_CFG(0x10), RK3288_GRF_SOC_CON3); \
+ grf_writel(GMAC_CLK_TX_DL_CFG(0x30), RK3288_GRF_SOC_CON3); \
+ grf_writel(0xffffffff,RK3288_GRF_GPIO3D_E); \
+ grf_writel(grf_readl(RK3288_GRF_GPIO4B_E) | 0x3<<2<<16 | 0x3<<2, RK3288_GRF_GPIO4B_E); \
+ grf_writel(0xffffffff,RK3288_GRF_GPIO4A_E); \
+ }
+
+#define SET_RMII { \
+ grf_writel(GMAC_PHY_INTF_SEL_RMII, RK3288_GRF_SOC_CON1); \
+ grf_writel(GMAC_RMII_MODE, RK3288_GRF_SOC_CON1); \
+ }
+
+#define SET_RGMII_10M { \
+ grf_writel(GMAC_CLK_2_5M, RK3288_GRF_SOC_CON1); \
+ }
+
+#define SET_RGMII_100M { \
+ grf_writel(GMAC_CLK_25M, RK3288_GRF_SOC_CON1); \
+ }
+
+#define SET_RGMII_1000M { \
+ grf_writel(GMAC_CLK_125M, RK3288_GRF_SOC_CON1); \
+ }
+
+#define SET_RMII_10M { \
+ grf_writel(GMAC_RMII_CLK_2_5M, RK3288_GRF_SOC_CON1); \
+ grf_writel(GMAC_SPEED_10M, RK3288_GRF_SOC_CON1); \
+ }
+
+#define SET_RMII_100M { \
+ grf_writel(GMAC_RMII_CLK_25M, RK3288_GRF_SOC_CON1); \
+ grf_writel(GMAC_SPEED_100M, RK3288_GRF_SOC_CON1); \
+ }
+#else //3128
+#define SET_RGMII { \
+ grf_writel(GMAC_PHY_INTF_SEL_RGMII, RK312X_GRF_MAC_CON1); \
+ grf_writel(GMAC_RMII_MODE_CLR, RK312X_GRF_MAC_CON1); \
+ grf_writel(GMAC_RXCLK_DLY_ENABLE, RK312X_GRF_MAC_CON0); \
+ grf_writel(GMAC_TXCLK_DLY_ENABLE, RK312X_GRF_MAC_CON0); \
+ grf_writel(GMAC_CLK_RX_DL_CFG(0x10), RK312X_GRF_MAC_CON0); \
+ grf_writel(GMAC_CLK_TX_DL_CFG(0x30), RK312X_GRF_MAC_CON0); \
+ }
+
+#define SET_RMII { \
+ grf_writel(GMAC_PHY_INTF_SEL_RMII, RK312X_GRF_MAC_CON1); \
+ grf_writel(GMAC_RMII_MODE, RK312X_GRF_MAC_CON1); \
+ }
+
+#define SET_RGMII_10M { \
+ grf_writel(GMAC_CLK_2_5M, RK312X_GRF_MAC_CON1); \
+ }
+
+#define SET_RGMII_100M { \
+ grf_writel(GMAC_CLK_25M, RK312X_GRF_MAC_CON1); \
+ }
+
+#define SET_RGMII_1000M { \
+ grf_writel(GMAC_CLK_125M, RK312X_GRF_MAC_CON1); \
+ }
+
+#define SET_RMII_10M { \
+ grf_writel(GMAC_RMII_CLK_2_5M, RK312X_GRF_MAC_CON1); \
+ grf_writel(GMAC_SPEED_10M, RK312X_GRF_MAC_CON1); \
+ }
+
+#define SET_RMII_100M { \
+ grf_writel(GMAC_RMII_CLK_25M, RK312X_GRF_MAC_CON1); \
+ grf_writel(GMAC_SPEED_100M, RK312X_GRF_MAC_CON1); \
+ }
+