Change-Id: I1742823658aa46226e3112969d3eabc695921fb5
Signed-off-by: Feng Xiao <xf@rock-chips.com>
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
<&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
<&cru PLL_CPLL>, <&cru PLL_GPLL>,
<&cru PLL_NPLL>, <&cru PLL_MPLL>,
<&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
<&cru PLL_CPLL>, <&cru PLL_GPLL>,
<&cru PLL_NPLL>, <&cru PLL_MPLL>,
<&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
<&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
assigned-clock-rates =
<&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
<&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
assigned-clock-rates =
<0>, <0>,
<750000000>, <576000000>,
<594000000>, <594000000>,
<0>, <0>,
<750000000>, <576000000>,
<594000000>, <594000000>,
<375000000>, <288000000>,
<100000000>, <100000000>;
assigned-clock-parents =
<375000000>, <288000000>,
<100000000>, <100000000>;
assigned-clock-parents =
<&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
};
<&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
};