-non-zero __builtin_return_address values on X86.
-vector shift support + X86 backend.
-x86 JIT now detects core i7 and atom, autoconfiguring itself appropriately.
-x86-64 now uses red zone (unless -mno-red-zone option is specified).
-x86 backend GS segment -> addr space 256 (r62980)
-X86 backend now supports -disable-mmx.
-JIT supports exceptions on linux/x86-64 and linux/x86-64.
-JIT TLS support on x86-32 but not x86-64.
+<li>The "<a href="LangRef.html#int_returnaddress">llvm.returnaddress</a>"
+intrinsic (which is used to implement "__builtin_return_address") now supports
+non-zero stack depths on X86.</li>
+
+<li>The X86 backend now supports code generation of vector shift operations
+using SSE instructions.</li>
+
+<li>X86-64 code generation now takes advantage of red zone (unless
+-mno-red-zone option is specified).</li>
+
+<li>The X86 backend now supports using address space #256 in LLVM IR as a way of
+performing memory references off the GS segment register. This allows a
+front-end to take advantage of very low-level programming techniques when
+targetting X86 CPUs. See test/CodeGen/X86/movgs.ll for a simple example.</li>
+
+<li>The X86 backend now supports a <tt>-disable-mmx</tt> command line option to
+ prevent use of MMX even on chips that support it. This is important for cases
+ where code does not contain the proper "llvm.x86.mmx.emms" intrinsics.</li>
+
+<li>The X86 JIT now detects the new Intel "<a
+ href="http://en.wikipedia.org/wiki/Intel_Core_i7">Core i7</a>" and <a
+ href="http://en.wikipedia.org/wiki/Intel_Atom">Atom</a>" chips,
+ auto-configuring itself appropriately for the features of these chips.</li>
+
+<li>The JIT now supports exception handling constructs on Linux/X86-64 and
+ Darwin/x86-64.</li>
+<li>The JIT supports Thread Local Storage (TLS) on Linux/X86-32 but not yet on
+ X86-64.</li>