When transforming a vector_shuffle to a load, the base address must not be an undef.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50940 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index d2d76671e94993a59ed0e1629132c97d9e74a50f..307aeae1b22cc71af0d43a747b8dd05d43405800 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -6283,6 +6283,8 @@ static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask,
       return false;
     if (!Base) {
       Base = Elt.Val;
       return false;
     if (!Base) {
       Base = Elt.Val;

+      if (Base->getOpcode() == ISD::UNDEF)
+        return false;

       continue;
     }
     if (Elt.getOpcode() == ISD::UNDEF)
       continue;
     }
     if (Elt.getOpcode() == ISD::UNDEF)

diff --git a/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll b/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll
new file mode 100644 (file)
index 0000000..9bcd1f3
--- /dev/null
+++ b/test/CodeGen/X86/2008-05-09-ShuffleLoweringBug.ll
@@ -0,0 +1,10 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
+
+define fastcc void @glgVectorFloatConversion() nounwind  {
+       %tmp12745 = load <4 x float>* null, align 16            ; <<4 x float>> [#uses=1]
+       %tmp12773 = insertelement <4 x float> %tmp12745, float 1.000000e+00, i32 1              ; <<4 x float>> [#uses=1]
+       %tmp12774 = insertelement <4 x float> %tmp12773, float 0.000000e+00, i32 2              ; <<4 x float>> [#uses=1]
+       %tmp12775 = insertelement <4 x float> %tmp12774, float 1.000000e+00, i32 3              ; <<4 x float>> [#uses=1]
+       store <4 x float> %tmp12775, <4 x float>* null, align 16
+       unreachable
+}