+ class SimpleSpiller : public Spiller {
+ public:
+ bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap& vrm) {
+ DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
+ DEBUG(std::cerr << "********** Function: "
+ << mf.getFunction()->getName() << '\n');
+ const TargetMachine& tm = mf.getTarget();
+ const MRegisterInfo& mri = *tm.getRegisterInfo();
+
+ typedef DenseMap<bool, VirtReg2IndexFunctor> Loaded;
+ Loaded loaded;
+
+ for (MachineFunction::iterator mbbi = mf.begin(),
+ mbbe = mf.end(); mbbi != mbbe; ++mbbi) {
+ DEBUG(std::cerr << mbbi->getBasicBlock()->getName() << ":\n");
+ for (MachineBasicBlock::iterator mii = mbbi->begin(),
+ mie = mbbi->end(); mii != mie; ++mii) {
+ loaded.grow(mf.getSSARegMap()->getLastVirtReg());
+ for (unsigned i = 0,e = mii->getNumOperands(); i != e; ++i){
+ MachineOperand& mop = mii->getOperand(i);
+ if (mop.isRegister() && mop.getReg() &&
+ MRegisterInfo::isVirtualRegister(mop.getReg())) {
+ unsigned virtReg = mop.getReg();
+ unsigned physReg = vrm.getPhys(virtReg);
+ if (mop.isUse() &&
+ vrm.hasStackSlot(mop.getReg()) &&
+ !loaded[virtReg]) {
+ mri.loadRegFromStackSlot(
+ *mbbi,
+ mii,
+ physReg,
+ vrm.getStackSlot(virtReg),
+ mf.getSSARegMap()->getRegClass(virtReg));
+ loaded[virtReg] = true;
+ DEBUG(std::cerr << '\t';
+ prior(mii)->print(std::cerr, tm));
+ ++numLoads;
+ }
+ if (mop.isDef() &&
+ vrm.hasStackSlot(mop.getReg())) {
+ mri.storeRegToStackSlot(
+ *mbbi,
+ next(mii),
+ physReg,
+ vrm.getStackSlot(virtReg),
+ mf.getSSARegMap()->getRegClass(virtReg));
+ ++numStores;
+ }
+ mii->SetMachineOperandReg(i, physReg);
+ }
+ }
+ DEBUG(std::cerr << '\t'; mii->print(std::cerr, tm));
+ loaded.clear();
+ }
+ }
+ return true;
+ }
+ };
+