The TargetLoweringInfo object is owned by the TargetMachine. In the future, the
TargetMachine object may change, which may also change the TargetLoweringInfo
object.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183356
91177308-0d34-0410-b5e6-
96231b3b80d8
/// function that is used when lowering a region of the function.
///
class FunctionLoweringInfo {
/// function that is used when lowering a region of the function.
///
class FunctionLoweringInfo {
+ const TargetMachine &TM;
+ const TargetLowering *TLI;
- const TargetLowering &TLI;
const Function *Fn;
MachineFunction *MF;
MachineRegisterInfo *RegInfo;
const Function *Fn;
MachineFunction *MF;
MachineRegisterInfo *RegInfo;
/// there's no other convenient place for it to live right now.
std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
/// there's no other convenient place for it to live right now.
std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
- explicit FunctionLoweringInfo(const TargetLowering &TLI);
+ explicit FunctionLoweringInfo(const TargetMachine &TM);
/// set - Initialize this FunctionLoweringInfo with the given Function
/// and its associated MachineFunction.
/// set - Initialize this FunctionLoweringInfo with the given Function
/// and its associated MachineFunction.
-FunctionLoweringInfo::FunctionLoweringInfo(const TargetLowering &tli)
- : TLI(tli) {
+FunctionLoweringInfo::FunctionLoweringInfo(const TargetMachine &TM)
+ : TM(TM), TLI(0) {
}
void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf) {
Fn = &fn;
MF = &mf;
RegInfo = &MF->getRegInfo();
}
void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf) {
Fn = &fn;
MF = &mf;
RegInfo = &MF->getRegInfo();
+ TLI = TM.getTargetLowering();
// Check whether the function can return without sret-demotion.
SmallVector<ISD::OutputArg, 4> Outs;
// Check whether the function can return without sret-demotion.
SmallVector<ISD::OutputArg, 4> Outs;
- GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, TLI);
- CanLowerReturn = TLI.CanLowerReturn(Fn->getCallingConv(), *MF,
- Fn->isVarArg(),
- Outs, Fn->getContext());
+ GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI);
+ CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
+ Fn->isVarArg(),
+ Outs, Fn->getContext());
// Initialize the mapping of values to registers. This is only set up for
// instruction values that are used outside of the block that defines
// Initialize the mapping of values to registers. This is only set up for
// instruction values that are used outside of the block that defines
if (const AllocaInst *AI = dyn_cast<AllocaInst>(I))
if (const ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
Type *Ty = AI->getAllocatedType();
if (const AllocaInst *AI = dyn_cast<AllocaInst>(I))
if (const ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
Type *Ty = AI->getAllocatedType();
- uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
+ uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
- std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
+ std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
AI->getAlignment());
TySize *= CUI->getZExtValue(); // Get total allocated size.
AI->getAlignment());
TySize *= CUI->getZExtValue(); // Get total allocated size.
assert(PHIReg && "PHI node does not have an assigned virtual register!");
SmallVector<EVT, 4> ValueVTs;
assert(PHIReg && "PHI node does not have an assigned virtual register!");
SmallVector<EVT, 4> ValueVTs;
- ComputeValueVTs(TLI, PN->getType(), ValueVTs);
+ ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
EVT VT = ValueVTs[vti];
for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
EVT VT = ValueVTs[vti];
- unsigned NumRegisters = TLI.getNumRegisters(Fn->getContext(), VT);
+ unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
for (unsigned i = 0; i != NumRegisters; ++i)
BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
for (unsigned i = 0; i != NumRegisters; ++i)
BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
/// CreateReg - Allocate a single virtual register for the given type.
unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
/// CreateReg - Allocate a single virtual register for the given type.
unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
- return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
+ return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT));
}
/// CreateRegs - Allocate the appropriate number of virtual registers of
}
/// CreateRegs - Allocate the appropriate number of virtual registers of
///
unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
SmallVector<EVT, 4> ValueVTs;
///
unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
SmallVector<EVT, 4> ValueVTs;
- ComputeValueVTs(TLI, Ty, ValueVTs);
+ ComputeValueVTs(*TLI, Ty, ValueVTs);
unsigned FirstReg = 0;
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
EVT ValueVT = ValueVTs[Value];
unsigned FirstReg = 0;
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
EVT ValueVT = ValueVTs[Value];
- MVT RegisterVT = TLI.getRegisterType(Ty->getContext(), ValueVT);
+ MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
- unsigned NumRegs = TLI.getNumRegisters(Ty->getContext(), ValueVT);
+ unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
for (unsigned i = 0; i != NumRegs; ++i) {
unsigned R = CreateReg(RegisterVT);
if (!FirstReg) FirstReg = R;
for (unsigned i = 0; i != NumRegs; ++i) {
unsigned R = CreateReg(RegisterVT);
if (!FirstReg) FirstReg = R;
return;
SmallVector<EVT, 1> ValueVTs;
return;
SmallVector<EVT, 1> ValueVTs;
- ComputeValueVTs(TLI, Ty, ValueVTs);
+ ComputeValueVTs(*TLI, Ty, ValueVTs);
assert(ValueVTs.size() == 1 &&
"PHIs with non-vector integer types should have a single VT.");
EVT IntVT = ValueVTs[0];
assert(ValueVTs.size() == 1 &&
"PHIs with non-vector integer types should have a single VT.");
EVT IntVT = ValueVTs[0];
- if (TLI.getNumRegisters(PN->getContext(), IntVT) != 1)
+ if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
- IntVT = TLI.getTypeToTransformTo(PN->getContext(), IntVT);
+ IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
unsigned BitWidth = IntVT.getSizeInBits();
unsigned DestReg = ValueMap[PN];
unsigned BitWidth = IntVT.getSizeInBits();
unsigned DestReg = ValueMap[PN];
SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
CodeGenOpt::Level OL) :
MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
CodeGenOpt::Level OL) :
MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
- FuncInfo(new FunctionLoweringInfo(TLI)),
+ FuncInfo(new FunctionLoweringInfo(TM)),
CurDAG(new SelectionDAG(tm, OL)),
SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
GFI(),
CurDAG(new SelectionDAG(tm, OL)),
SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
GFI(),