Check bits for preferred register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56384
91177308-0d34-0410-b5e6-
96231b3b80d8
unsigned FreeRegInactiveCount = 0;
// If copy coalescer has assigned a "preferred" register, check if it's
unsigned FreeRegInactiveCount = 0;
// If copy coalescer has assigned a "preferred" register, check if it's
+ // available first. Coalescer can create new earlyclobber interferences,
+ // so we need to check that.
- if (prt_->isRegAvail(cur->preference) && RC->contains(cur->preference)) {
+ if (prt_->isRegAvail(cur->preference) &&
+ RC->contains(cur->preference) &&
+ noEarlyClobberConflict(cur, cur->preference)) {
DOUT << "\t\tassigned the preferred register: "
<< tri_->getName(cur->preference) << "\n";
return cur->preference;
DOUT << "\t\tassigned the preferred register: "
<< tri_->getName(cur->preference) << "\n";
return cur->preference;
DOUT << " and "; DstInt.print(DOUT, tri_);
DOUT << ": ";
DOUT << " and "; DstInt.print(DOUT, tri_);
DOUT << ": ";
+ // If one interval is earlyclobber and the other is overlaps-earlyclobber,
+ // we cannot coalesce them.
+ if ((SrcInt.isEarlyClobber && DstInt.overlapsEarlyClobber) ||
+ (DstInt.isEarlyClobber && SrcInt.overlapsEarlyClobber)) {
+ DOUT << "\t\tCannot join due to earlyclobber.";
+ return false;
+ }
+
// Check if it is necessary to propagate "isDead" property.
if (!isExtSubReg && !isInsSubReg) {
MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
// Check if it is necessary to propagate "isDead" property.
if (!isExtSubReg && !isInsSubReg) {
MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
if (TargetRegisterInfo::isVirtualRegister(DstReg))
RemoveUnnecessaryKills(DstReg, *ResDstInt);
if (TargetRegisterInfo::isVirtualRegister(DstReg))
RemoveUnnecessaryKills(DstReg, *ResDstInt);
+ // Merge the earlyclobber bits.
+ ResDstInt->isEarlyClobber |= ResSrcInt->isEarlyClobber;
+ ResDstInt->overlapsEarlyClobber |= ResSrcInt->overlapsEarlyClobber;
+
if (isInsSubReg)
// Avoid:
// r1024 = op
if (isInsSubReg)
// Avoid:
// r1024 = op