The dag combiner can produce a shift of i1 when folding icmp i1's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53030
91177308-0d34-0410-b5e6-
96231b3b80d8
assert(VT == N1.getValueType() &&
"Shift operators return type must be the same as their first arg");
assert(VT.isInteger() && N2.getValueType().isInteger() &&
assert(VT == N1.getValueType() &&
"Shift operators return type must be the same as their first arg");
assert(VT.isInteger() && N2.getValueType().isInteger() &&
- VT != MVT::i1 && "Shifts only work on integers");
+ "Shifts only work on integers");
+
+ // Always fold shifts of i1 values so the code generator doesn't need to
+ // handle them. Since we know the size of the shift has to be less than the
+ // size of the value, the shift/rotate count is guaranteed to be zero.
+ if (VT == MVT::i1)
+ return N1;
break;
case ISD::FP_ROUND_INREG: {
MVT EVT = cast<VTSDNode>(N2)->getVT();
break;
case ISD::FP_ROUND_INREG: {
MVT EVT = cast<VTSDNode>(N2)->getVT();