+void memcpy_img_info(struct rga_img_info_t *dst, struct rga_img_info_32_t *src)\r
+{\r
+ dst->yrgb_addr = src->yrgb_addr; /* yrgb mem addr */\r
+ dst->uv_addr = src->uv_addr; /* cb/cr mem addr */\r
+ dst->v_addr = src->v_addr; /* cr mem addr */\r
+ dst->format = src->format; //definition by RK_FORMAT\r
+\r
+ dst->act_w = src->act_w;\r
+ dst->act_h = src->act_h;\r
+ dst->x_offset = src->x_offset;\r
+ dst->y_offset = src->y_offset;\r
+\r
+ dst->vir_w = src->vir_w;\r
+ dst->vir_h = src->vir_h;\r
+ dst->endian_mode = src->endian_mode; //for BPP\r
+ dst->alpha_swap = src->alpha_swap;\r
+}\r
+void RGA_MSG_2_RGA2_MSG_32(struct rga_req_32 *req_rga, struct rga2_req *req)\r
+{\r
+ u16 alpha_mode_0, alpha_mode_1;\r
+ if (req_rga->render_mode == 6)\r
+ req->render_mode = update_palette_table_mode;\r
+ else if (req_rga->render_mode == 7)\r
+ req->render_mode = update_patten_buff_mode;\r
+ else if (req_rga->render_mode == 5)\r
+ req->render_mode = bitblt_mode;\r
+ else\r
+ req->render_mode = req_rga->render_mode;\r
+ memcpy_img_info(&req->src, &req_rga->src);\r
+ memcpy_img_info(&req->dst, &req_rga->dst);\r
+ memcpy_img_info(&req->pat, &req_rga->pat);\r
+ memcpy_img_info(&req->src1,&req_rga->pat);\r
+ format_name_convert(&req->src.format, req_rga->src.format);\r
+ format_name_convert(&req->dst.format, req_rga->dst.format);\r
+ if(req_rga->rotate_mode == 1) {\r
+ if(req_rga->sina == 0 && req_rga->cosa == 65536) {\r
+ req->rotate_mode = 0;\r
+ }\r
+ else if (req_rga->sina == 65536 && req_rga->cosa == 0) {\r
+ req->rotate_mode = 1;\r
+ req->dst.x_offset = req_rga->dst.x_offset - req_rga->dst.act_h + 1;\r
+ req->dst.act_w = req_rga->dst.act_h;\r
+ req->dst.act_h = req_rga->dst.act_w;\r
+ }\r
+ else if (req_rga->sina == 0 && req_rga->cosa == -65536) {\r
+ req->rotate_mode = 2;\r
+ req->dst.x_offset = req_rga->dst.x_offset - req_rga->dst.act_w + 1;\r
+ req->dst.y_offset = req_rga->dst.y_offset - req_rga->dst.act_h + 1;\r
+ }\r
+ else if (req_rga->sina == -65536 && req_rga->cosa == 0) {\r
+ req->rotate_mode = 3;\r
+ req->dst.y_offset = req_rga->dst.y_offset - req_rga->dst.act_w + 1;\r
+ req->dst.act_w = req_rga->dst.act_h;\r
+ req->dst.act_h = req_rga->dst.act_w;\r
+ }\r
+ }\r
+ else if (req_rga->rotate_mode == 2)\r
+ {\r
+ req->rotate_mode = (1 << 4);\r
+ }\r
+ else if (req_rga->rotate_mode == 3)\r
+ {\r
+ req->rotate_mode = (2 << 4);\r
+ }\r
+ else {\r
+ req->rotate_mode = 0;\r
+ }\r
+ if((req->dst.act_w > 2048) && (req->src.act_h < req->dst.act_h))\r
+ req->scale_bicu_mode |= (1<<4);\r
+ req->LUT_addr = req_rga->LUT_addr;\r
+ req->rop_mask_addr = req_rga->rop_mask_addr;\r
+ req->bitblt_mode = req_rga->bsfilter_flag;\r
+ req->src_a_global_val = req_rga->alpha_global_value;\r
+ req->dst_a_global_val = 0;\r
+ req->rop_code = req_rga->rop_code;\r
+ req->rop_mode = 0;\r
+ req->color_fill_mode = req_rga->color_fill_mode;\r
+ req->color_key_min = req_rga->color_key_min;\r
+ req->color_key_max = req_rga->color_key_max;\r
+ req->fg_color = req_rga->fg_color;\r
+ req->bg_color = req_rga->bg_color;\r
+ memcpy(&req->gr_color, &req_rga->gr_color, sizeof(req_rga->gr_color));\r
+ req->palette_mode = req_rga->palette_mode;\r
+ req->yuv2rgb_mode = req_rga->yuv2rgb_mode + 1;\r
+ req->endian_mode = req_rga->endian_mode;\r
+ req->rgb2yuv_mode = 0;\r
+ req->fading_alpha_value = 0;\r
+ req->fading_r_value = req_rga->fading.r;\r
+ req->fading_g_value = req_rga->fading.g;\r
+ req->fading_b_value = req_rga->fading.b;\r
+ req->alpha_rop_flag = 0;\r
+ req->alpha_rop_flag |= (((req_rga->alpha_rop_flag & 1))); // alpha_rop_enable\r
+ req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 1) & 1) << 1); // rop_enable\r
+ req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 2) & 1) << 2); // fading_enable\r
+ req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 4) & 1) << 3); // alpha_cal_mode_sel\r
+ req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 5) & 1) << 6); // dst_dither_down\r
+ req->alpha_rop_flag |= (((req_rga->alpha_rop_flag >> 6) & 1) << 7); // gradient fill mode sel\r
+ if(((req_rga->alpha_rop_flag) & 1)) {\r
+ if((req_rga->alpha_rop_flag >> 3) & 1) {\r
+ switch(req_rga->PD_mode)\r
+ {\r
+ case 0: //dst = 0\r
+ break;\r
+ case 1: //dst = src\r
+ break;\r
+ case 2: //dst = dst\r
+ break;\r
+ case 3: //dst = (256*sc + (256 - sa)*dc) >> 8\r
+ if((req_rga->alpha_rop_mode & 3) == 0) {\r
+ alpha_mode_0 = 0x3818;\r
+ alpha_mode_1 = 0x3818;\r
+ }\r
+ else if ((req_rga->alpha_rop_mode & 3) == 1) {\r
+ alpha_mode_0 = 0x381A;\r
+ alpha_mode_1 = 0x381A;\r
+ }\r
+ else if ((req_rga->alpha_rop_mode & 3) == 2) {\r
+ alpha_mode_0 = 0x381C;\r
+ alpha_mode_1 = 0x381C;\r
+ }\r
+ else {\r
+ alpha_mode_0 = 0x381A;\r
+ alpha_mode_1 = 0x381A;\r
+ }\r
+ req->alpha_mode_0 = alpha_mode_0;\r
+ req->alpha_mode_1 = alpha_mode_1;\r
+ break;\r
+ case 4: //dst = (sc*(256-da) + 256*dc) >> 8\r
+ break;\r
+ case 5: //dst = (da*sc) >> 8\r
+ break;\r
+ case 6: //dst = (sa*dc) >> 8\r
+ break;\r
+ case 7: //dst = ((256-da)*sc) >> 8\r
+ break;\r
+ case 8: //dst = ((256-sa)*dc) >> 8\r
+ break;\r
+ case 9: //dst = (da*sc + (256-sa)*dc) >> 8\r
+ req->alpha_mode_0 = 0x3848;\r
+ req->alpha_mode_1 = 0x3848;\r
+ break;\r
+ case 10://dst = ((256-da)*sc + (sa*dc)) >> 8\r
+ break;\r
+ case 11://dst = ((256-da)*sc + (256-sa)*dc) >> 8;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+ }\r
+ else {\r
+ if((req_rga->alpha_rop_mode & 3) == 0) {\r
+ req->alpha_mode_0 = 0x3848;\r
+ req->alpha_mode_1 = 0x3848;\r
+ }\r
+ else if ((req_rga->alpha_rop_mode & 3) == 1) {\r
+ req->alpha_mode_0 = 0x483A;\r
+ req->alpha_mode_1 = 0x483A;\r
+ }\r
+ else if ((req_rga->alpha_rop_mode & 3) == 2) {\r
+ req->alpha_mode_0 = 0x384C;\r
+ req->alpha_mode_1 = 0x384C;\r
+ }\r
+ }\r
+ }\r
+ if (req_rga->mmu_info.mmu_en && (req_rga->mmu_info.mmu_flag & 1) == 1) {\r
+ req->mmu_info.src0_mmu_flag = 1;\r
+ req->mmu_info.dst_mmu_flag = 1;\r
+ if (req_rga->mmu_info.mmu_flag >> 31) {\r
+ req->mmu_info.src0_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 8) & 1);\r
+ req->mmu_info.src1_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 9) & 1);\r
+ req->mmu_info.dst_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 10) & 1);\r
+ req->mmu_info.els_mmu_flag = ((req_rga->mmu_info.mmu_flag >> 11) & 1);\r
+ }\r
+ else {\r
+ if (req_rga->src.yrgb_addr >= 0xa0000000) {\r
+ req->mmu_info.src0_mmu_flag = 0;\r
+ req->src.yrgb_addr = req_rga->src.yrgb_addr - 0x60000000;\r
+ req->src.uv_addr = req_rga->src.uv_addr - 0x60000000;\r
+ req->src.v_addr = req_rga->src.v_addr - 0x60000000;\r
+ }\r
+ if (req_rga->dst.yrgb_addr >= 0xa0000000) {\r
+ req->mmu_info.dst_mmu_flag = 0;\r
+ req->dst.yrgb_addr = req_rga->dst.yrgb_addr - 0x60000000;\r
+ }\r
+ }\r
+ }\r
+}\r