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rockchip: iommu: change compatible name for iommu in rk3288.dtsi
author
xxm
<xxm@rock-chips.com>
Fri, 8 Aug 2014 03:02:50 +0000
(11:02 +0800)
committer
xxm
<xxm@rock-chips.com>
Fri, 8 Aug 2014 03:02:50 +0000
(11:02 +0800)
arch/arm/boot/dts/rk3288.dtsi
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diff --git
a/arch/arm/boot/dts/rk3288.dtsi
b/arch/arm/boot/dts/rk3288.dtsi
index 6353a8babb727b628e79cb2e8bb2a30cde0fb78d..763ea0b9a398fc228ba02fe772a7d9247929eab1 100755
(executable)
--- a/
arch/arm/boot/dts/rk3288.dtsi
+++ b/
arch/arm/boot/dts/rk3288.dtsi
@@
-1166,7
+1166,7
@@
iep_mmu {
dbgname = "iep";
iep_mmu {
dbgname = "iep";
- compatible = "
iommu
,iep_mmu";
+ compatible = "
rockchip
,iep_mmu";
reg = <0xff900800 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
reg = <0xff900800 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
@@
-1174,7
+1174,7
@@
vip_mmu {
dbgname = "vip";
vip_mmu {
dbgname = "vip";
- compatible = "
iommu
,vip_mmu";
+ compatible = "
rockchip
,vip_mmu";
reg = <0xff950800 0x100>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vip_mmu";
reg = <0xff950800 0x100>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vip_mmu";
@@
-1182,7
+1182,7
@@
vopb_mmu {
dbgname = "vopb";
vopb_mmu {
dbgname = "vopb";
- compatible = "
iommu
,vopb_mmu";
+ compatible = "
rockchip
,vopb_mmu";
reg = <0xff930300 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopb_mmu";
reg = <0xff930300 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopb_mmu";
@@
-1190,7
+1190,7
@@
vopl_mmu {
dbgname = "vopl";
vopl_mmu {
dbgname = "vopl";
- compatible = "
iommu
,vopl_mmu";
+ compatible = "
rockchip
,vopl_mmu";
reg = <0xff940300 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
reg = <0xff940300 0x100>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vopl_mmu";
@@
-1198,7
+1198,7
@@
hevc_mmu {
dbgname = "hevc";
hevc_mmu {
dbgname = "hevc";
- compatible = "
iommu
,hevc_mmu";
+ compatible = "
rockchip
,hevc_mmu";
reg = <0xff9c0440 0x100>,
<0xff9c0480 0x100>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff9c0440 0x100>,
<0xff9c0480 0x100>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
@@
-1207,7
+1207,7
@@
vpu_mmu {
dbgname = "vpu";
vpu_mmu {
dbgname = "vpu";
- compatible = "
iommu
,vpu_mmu";
+ compatible = "
rockchip
,vpu_mmu";
reg = <0xff9a0800 0x100>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
reg = <0xff9a0800 0x100>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
@@
-1215,7
+1215,7
@@
isp_mmu {
dbgname = "isp_mmu";
isp_mmu {
dbgname = "isp_mmu";
- compatible = "
iommu
,isp_mmu";
+ compatible = "
rockchip
,isp_mmu";
reg = <0xff914000 0x100>,
<0xff915000 0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xff914000 0x100>,
<0xff915000 0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;