+
+ // Accum registers
+ def LO0 : Register<"ac0"> {
+ let Aliases = [LO];
+ }
+ def HI0 : Register<"hi0"> {
+ let Aliases = [HI];
+ }
+ def LO1 : Register<"ac1">;
+ def HI1 : Register<"hi1">;
+ def LO2 : Register<"ac2">;
+ def HI2 : Register<"hi2">;
+ def LO3 : Register<"ac3">;
+ def HI3 : Register<"hi3">;
+
+ let SubRegIndices = [sub_32] in {
+ def LO0_64 : RegisterWithSubRegs<"ac0", [LO0]> {
+ let Aliases = [LO64];
+ }
+ def HI0_64 : RegisterWithSubRegs<"hi0", [HI0]> {
+ let Aliases = [HI64];
+ }
+ def LO1_64 : RegisterWithSubRegs<"ac1", [LO1]>;
+ def HI1_64 : RegisterWithSubRegs<"hi1", [HI1]>;
+ def LO2_64 : RegisterWithSubRegs<"ac2", [LO2]>;
+ def HI2_64 : RegisterWithSubRegs<"hi2", [HI2]>;
+ def LO3_64 : RegisterWithSubRegs<"ac3", [LO3]>;
+ def HI3_64 : RegisterWithSubRegs<"hi3", [HI3]>;
+ }
+
+ def DSPCtrl : Register<"dspctrl">;