In preparation for the addition of other SIMD ISA extensions (such as QPX) we
need to make sure that all Altivec patterns are properly predicated on having
Altivec support.
No functionality change intended (one test case needed to be updated b/c it
assumed that Altivec intrinsics would be supported without enabling Altivec
support).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177152
91177308-0d34-0410-b5e6-
96231b3b80d8
//===----------------------------------------------------------------------===//
// Instruction Definitions.
//===----------------------------------------------------------------------===//
// Instruction Definitions.
+def HasAltivec : Predicate<"PPCSubTarget.hasAltivec()">;
+let Predicates = [HasAltivec] in {
+
def DSS : DSS_Form<822, (outs),
(ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
"dss $STRM", LdStLoad /*FIXME*/, []>;
def DSS : DSS_Form<822, (outs),
(ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
"dss $STRM", LdStLoad /*FIXME*/, []>;
(VRFIZ VRRC:$vA)>;
def : Pat<(v4f32 (fnearbyint (v4f32 VRRC:$vA))),
(VRFIN VRRC:$vA)>;
(VRFIZ VRRC:$vA)>;
def : Pat<(v4f32 (fnearbyint (v4f32 VRRC:$vA))),
(VRFIN VRRC:$vA)>;
-; RUN: llc < %s -march=ppc64 | grep dst | count 4
+; RUN: llc < %s -march=ppc64 -mattr=+altivec | grep dst | count 4
define hidden void @_Z4borkPc(i8* %image) {
entry:
define hidden void @_Z4borkPc(i8* %image) {
entry: