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[Sparc]: Use cmp instruction instead of subcc to compare integers.
author
Venkatraman Govindaraju
<venkatra@cs.wisc.edu>
Fri, 7 Jun 2013 00:03:36 +0000
(
00:03
+0000)
committer
Venkatraman Govindaraju
<venkatra@cs.wisc.edu>
Fri, 7 Jun 2013 00:03:36 +0000
(
00:03
+0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183463
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/Sparc/SparcISelLowering.cpp
patch
|
blob
|
history
lib/Target/Sparc/SparcInstr64Bit.td
patch
|
blob
|
history
lib/Target/Sparc/SparcInstrInfo.td
patch
|
blob
|
history
test/CodeGen/SPARC/2011-01-11-CC.ll
patch
|
blob
|
history
test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
patch
|
blob
|
history
test/CodeGen/SPARC/64bit.ll
patch
|
blob
|
history
test/CodeGen/SPARC/64cond.ll
patch
|
blob
|
history
diff --git
a/lib/Target/Sparc/SparcISelLowering.cpp
b/lib/Target/Sparc/SparcISelLowering.cpp
index 8dd29161db5d50b69d9c745ff70c0340dd8bece0..3cd9a74bdeed4574e8e6d03bf168cfe1661654d0 100644
(file)
--- a/
lib/Target/Sparc/SparcISelLowering.cpp
+++ b/
lib/Target/Sparc/SparcISelLowering.cpp
@@
-1575,9
+1575,7
@@
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
// Get the condition flag.
SDValue CompareFlag;
if (LHS.getValueType().isInteger()) {
// Get the condition flag.
SDValue CompareFlag;
if (LHS.getValueType().isInteger()) {
- EVT VTs[] = { LHS.getValueType(), MVT::Glue };
- SDValue Ops[2] = { LHS, RHS };
- CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
+ CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
// 32-bit compares use the icc flags, 64-bit uses the xcc flags.
Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
// 32-bit compares use the icc flags, 64-bit uses the xcc flags.
Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
@@
-1605,10
+1603,7
@@
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
SDValue CompareFlag;
if (LHS.getValueType().isInteger()) {
SDValue CompareFlag;
if (LHS.getValueType().isInteger()) {
- // subcc returns a value
- EVT VTs[] = { LHS.getValueType(), MVT::Glue };
- SDValue Ops[2] = { LHS, RHS };
- CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
+ CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
Opc = LHS.getValueType() == MVT::i32 ?
SPISD::SELECT_ICC : SPISD::SELECT_XCC;
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
Opc = LHS.getValueType() == MVT::i32 ?
SPISD::SELECT_ICC : SPISD::SELECT_XCC;
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
diff --git
a/lib/Target/Sparc/SparcInstr64Bit.td
b/lib/Target/Sparc/SparcInstr64Bit.td
index ed7f05f3c4b9f1753b8d2fd0fb3230233867e9ce..21ac4a7dc169e15eb25a4cc32de202ea6f209a5c 100644
(file)
--- a/
lib/Target/Sparc/SparcInstr64Bit.td
+++ b/
lib/Target/Sparc/SparcInstr64Bit.td
@@
-160,7
+160,7
@@
def : Pat<(sube i64:$a, i64:$b), (SUBXrr $a, $b)>;
def : Pat<(addc i64:$a, i64:$b), (ADDCCrr $a, $b)>;
def : Pat<(subc i64:$a, i64:$b), (SUBCCrr $a, $b)>;
def : Pat<(addc i64:$a, i64:$b), (ADDCCrr $a, $b)>;
def : Pat<(subc i64:$a, i64:$b), (SUBCCrr $a, $b)>;
-def : Pat<(SPcmpicc i64:$a, i64:$b), (
SUBCC
rr $a, $b)>;
+def : Pat<(SPcmpicc i64:$a, i64:$b), (
CMP
rr $a, $b)>;
// Register-immediate instructions.
// Register-immediate instructions.
@@
-171,7
+171,7
@@
def : Pat<(xor i64:$a, (i64 simm13:$b)), (XORri $a, (as_i32imm $b))>;
def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>;
def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>;
def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>;
def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>;
-def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (
SUBCC
ri $a, (as_i32imm $b))>;
+def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (
CMP
ri $a, (as_i32imm $b))>;
} // Predicates = [Is64Bit]
} // Predicates = [Is64Bit]
diff --git
a/lib/Target/Sparc/SparcInstrInfo.td
b/lib/Target/Sparc/SparcInstrInfo.td
index b2f98548c5114677fd8b4ed72e7fce4bc604ad29..663947cbe6c1e1924a22db95831fc506009a900a 100644
(file)
--- a/
lib/Target/Sparc/SparcInstrInfo.td
+++ b/
lib/Target/Sparc/SparcInstrInfo.td
@@
-89,6
+89,8
@@
def calltarget : Operand<i32>;
let PrintMethod = "printCCOperand" in
def CCOp : Operand<i32>;
let PrintMethod = "printCCOperand" in
def CCOp : Operand<i32>;
+def SDTSPcmpicc :
+SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
def SDTSPcmpfcc :
SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
def SDTSPbrcc :
def SDTSPcmpfcc :
SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
def SDTSPbrcc :
@@
-100,7
+102,7
@@
SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
def SDTSPITOF :
SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
def SDTSPITOF :
SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
-def SPcmpicc : SDNode<"SPISD::CMPICC", SDT
IntBinOp
, [SDNPOutGlue]>;
+def SPcmpicc : SDNode<"SPISD::CMPICC", SDT
SPcmpicc
, [SDNPOutGlue]>;
def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
@@
-476,8
+478,18
@@
defm SUB : F3_12 <"sub" , 0b000100, sub>;
let Uses = [ICC] in
defm SUBX : F3_12 <"subx" , 0b001100, sube>;
let Uses = [ICC] in
defm SUBX : F3_12 <"subx" , 0b001100, sube>;
-let Defs = [ICC] in
- defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
+let Defs = [ICC] in {
+ defm SUBCC : F3_12 <"subcc", 0b010100, subc>;
+
+ def CMPrr : F3_1<2, 0b010100,
+ (outs), (ins IntRegs:$b, IntRegs:$c),
+ "cmp $b, $c",
+ [(SPcmpicc i32:$b, i32:$c)]>;
+ def CMPri : F3_1<2, 0b010100,
+ (outs), (ins IntRegs:$b, i32imm:$c),
+ "cmp $b, $c",
+ [(SPcmpicc i32:$b, (i32 simm13:$c))]>;
+}
let Uses = [ICC], Defs = [ICC] in
def SUBXCCrr: F3_1<2, 0b011100,
let Uses = [ICC], Defs = [ICC] in
def SUBXCCrr: F3_1<2, 0b011100,
@@
-795,11
+807,6
@@
def : Pat<(i32 simm13:$val),
def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
-// subc
-def : Pat<(subc i32:$b, i32:$c),
- (SUBCCrr $b, $c)>;
-def : Pat<(subc i32:$b, simm13:$val),
- (SUBCCri $b, imm:$val)>;
// Global addresses, constant pool entries
def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
// Global addresses, constant pool entries
def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
diff --git
a/test/CodeGen/SPARC/2011-01-11-CC.ll
b/test/CodeGen/SPARC/2011-01-11-CC.ll
index f676fd836947bdbad52c7720a3c875f9f08c10cf..599b451993e2d06bdece5b081d8df7a2c6169107 100644
(file)
--- a/
test/CodeGen/SPARC/2011-01-11-CC.ll
+++ b/
test/CodeGen/SPARC/2011-01-11-CC.ll
@@
-21,10
+21,10
@@
entry:
define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline {
entry:
; V8: test_select_int_icc
define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline {
entry:
; V8: test_select_int_icc
-; V8:
subcc
+; V8:
cmp
; V8: {{be|bne}}
; V9: test_select_int_icc
; V8: {{be|bne}}
; V9: test_select_int_icc
-; V9:
subcc
+; V9:
cmp
; V9-NOT: {{be|bne}}
; V9: mov{{e|ne}} %icc
%0 = icmp eq i32 %a, 0
; V9-NOT: {{be|bne}}
; V9: mov{{e|ne}} %icc
%0 = icmp eq i32 %a, 0
@@
-36,10
+36,10
@@
entry:
define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline {
entry:
; V8: test_select_fp_icc
define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline {
entry:
; V8: test_select_fp_icc
-; V8:
subcc
+; V8:
cmp
; V8: {{be|bne}}
; V9: test_select_fp_icc
; V8: {{be|bne}}
; V9: test_select_fp_icc
-; V9:
subcc
+; V9:
cmp
; V9-NOT: {{be|bne}}
; V9: fmovs{{e|ne}} %icc
%0 = icmp eq i32 %a, 0
; V9-NOT: {{be|bne}}
; V9: fmovs{{e|ne}} %icc
%0 = icmp eq i32 %a, 0
@@
-50,10
+50,10
@@
entry:
define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline {
entry:
; V8: test_select_dfp_icc
define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline {
entry:
; V8: test_select_dfp_icc
-; V8:
subcc
+; V8:
cmp
; V8: {{be|bne}}
; V9: test_select_dfp_icc
; V8: {{be|bne}}
; V9: test_select_dfp_icc
-; V9:
subcc
+; V9:
cmp
; V9-NOT: {{be|bne}}
; V9: fmovd{{e|ne}} %icc
%0 = icmp eq i32 %a, 0
; V9-NOT: {{be|bne}}
; V9: fmovd{{e|ne}} %icc
%0 = icmp eq i32 %a, 0
diff --git
a/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
b/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
index 89981a8d8e1d914fb0227d357304f39085e39a3d..b39c355fbdcdf3aa2562b0980fb0e311d7eb1abb 100644
(file)
--- a/
test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
+++ b/
test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
@@
-40,7
+40,7
@@
bb: ; preds = %entry, %bb
%a_addr.0 = add i32 %.pn, %a_addr.18
%3 = add nsw i32 %1, 1
%exitcond = icmp eq i32 %3, %b
%a_addr.0 = add i32 %.pn, %a_addr.18
%3 = add nsw i32 %1, 1
%exitcond = icmp eq i32 %3, %b
-;CHECK:
subcc
+;CHECK:
cmp
;CHECK: bne
;CHECK-NOT: nop
br i1 %exitcond, label %bb5, label %bb
;CHECK: bne
;CHECK-NOT: nop
br i1 %exitcond, label %bb5, label %bb
@@
-57,7
+57,7
@@
entry:
;CHECK: test_inlineasm
;CHECK: sethi
;CHECK: !NO_APP
;CHECK: test_inlineasm
;CHECK: sethi
;CHECK: !NO_APP
-;CHECK-NEXT:
subcc
+;CHECK-NEXT:
cmp
;CHECK-NEXT: bg
;CHECK-NEXT: nop
tail call void asm sideeffect "sethi 0, %g0", ""() nounwind
;CHECK-NEXT: bg
;CHECK-NEXT: nop
tail call void asm sideeffect "sethi 0, %g0", ""() nounwind
diff --git
a/test/CodeGen/SPARC/64bit.ll
b/test/CodeGen/SPARC/64bit.ll
index 4eb25536650eedfd6db434cd30cfdb4f10a32d08..c8569419a21eea44fb069eae05408fd11d05b431 100644
(file)
--- a/
test/CodeGen/SPARC/64bit.ll
+++ b/
test/CodeGen/SPARC/64bit.ll
@@
-230,7
+230,7
@@
entry:
declare void @g(i8*)
; CHECK: expand_setcc
declare void @g(i8*)
; CHECK: expand_setcc
-; CHECK:
subcc %i0, 1,
+; CHECK:
cmp %i0, 1
; CHECK: movl %xcc, 1,
define i32 @expand_setcc(i64 %a) {
%cond = icmp sle i64 %a, 0
; CHECK: movl %xcc, 1,
define i32 @expand_setcc(i64 %a) {
%cond = icmp sle i64 %a, 0
diff --git
a/test/CodeGen/SPARC/64cond.ll
b/test/CodeGen/SPARC/64cond.ll
index 88b476d1a24261dc859ca2036f16c9aca98556c1..f0f6f9e749a48d4bac76f0c3fdf2163dfce2912c 100644
(file)
--- a/
test/CodeGen/SPARC/64cond.ll
+++ b/
test/CodeGen/SPARC/64cond.ll
@@
-2,7
+2,7
@@
; Testing 64-bit conditionals. The sparc64 triple is an alias for sparcv9.
; CHECK: cmpri
; Testing 64-bit conditionals. The sparc64 triple is an alias for sparcv9.
; CHECK: cmpri
-; CHECK:
subcc
%i1, 1
+; CHECK:
cmp
%i1, 1
; CHECK: bpe %xcc,
define void @cmpri(i64* %p, i64 %x) {
entry:
; CHECK: bpe %xcc,
define void @cmpri(i64* %p, i64 %x) {
entry:
@@
-18,7
+18,7
@@
if.end:
}
; CHECK: cmprr
}
; CHECK: cmprr
-; CHECK:
subcc
%i1, %i2
+; CHECK:
cmp
%i1, %i2
; CHECK: bpgu %xcc,
define void @cmprr(i64* %p, i64 %x, i64 %y) {
entry:
; CHECK: bpgu %xcc,
define void @cmprr(i64* %p, i64 %x, i64 %y) {
entry:
@@
-34,7
+34,7
@@
if.end:
}
; CHECK: selecti32_xcc
}
; CHECK: selecti32_xcc
-; CHECK:
subcc
%i0, %i1
+; CHECK:
cmp
%i0, %i1
; CHECK: movg %xcc, %i2, %i3
; CHECK: restore %g0, %i3, %o0
define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) {
; CHECK: movg %xcc, %i2, %i3
; CHECK: restore %g0, %i3, %o0
define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) {
@@
-45,7
+45,7
@@
entry:
}
; CHECK: selecti64_xcc
}
; CHECK: selecti64_xcc
-; CHECK:
subcc
%i0, %i1
+; CHECK:
cmp
%i0, %i1
; CHECK: movg %xcc, %i2, %i3
; CHECK: restore %g0, %i3, %o0
define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) {
; CHECK: movg %xcc, %i2, %i3
; CHECK: restore %g0, %i3, %o0
define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) {
@@
-56,7
+56,7
@@
entry:
}
; CHECK: selecti64_icc
}
; CHECK: selecti64_icc
-; CHECK:
subcc
%i0, %i1
+; CHECK:
cmp
%i0, %i1
; CHECK: movg %icc, %i2, %i3
; CHECK: restore %g0, %i3, %o0
define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) {
; CHECK: movg %icc, %i2, %i3
; CHECK: restore %g0, %i3, %o0
define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) {
@@
-78,7
+78,7
@@
entry:
}
; CHECK: selectf32_xcc
}
; CHECK: selectf32_xcc
-; CHECK:
subcc
%i0, %i1
+; CHECK:
cmp
%i0, %i1
; CHECK: fmovsg %xcc, %f5, %f7
; CHECK: fmovs %f7, %f1
define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
; CHECK: fmovsg %xcc, %f5, %f7
; CHECK: fmovs %f7, %f1
define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
@@
-89,7
+89,7
@@
entry:
}
; CHECK: selectf64_xcc
}
; CHECK: selectf64_xcc
-; CHECK:
subcc
%i0, %i1
+; CHECK:
cmp
%i0, %i1
; CHECK: fmovdg %xcc, %f4, %f6
; CHECK: fmovd %f6, %f0
define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) {
; CHECK: fmovdg %xcc, %f4, %f6
; CHECK: fmovd %f6, %f0
define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) {
@@
-101,7
+101,7
@@
entry:
; The MOVXCC instruction can't use %g0 for its tied operand.
; CHECK: select_consti64_xcc
; The MOVXCC instruction can't use %g0 for its tied operand.
; CHECK: select_consti64_xcc
-; CHECK:
subcc
+; CHECK:
cmp
; CHECK: movg %xcc, 123, %i0
define i64 @select_consti64_xcc(i64 %x, i64 %y) {
entry:
; CHECK: movg %xcc, 123, %i0
define i64 @select_consti64_xcc(i64 %x, i64 %y) {
entry: