Don't cache the instruction and register info from the TargetMachine, because
authorBill Wendling <isanbard@gmail.com>
Fri, 7 Jun 2013 20:42:15 +0000 (20:42 +0000)
committerBill Wendling <isanbard@gmail.com>
Fri, 7 Jun 2013 20:42:15 +0000 (20:42 +0000)
commitfc61b6f111af79662baf273c40593a1e8f4dc719
tree455c0fd93c8addc3c6c6801ccea7ea472fad371b
parent3ff0abfaabc2c7f604d490be587b9c27e7c91ac0
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183567 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/SystemZ/SystemZInstrInfo.cpp
lib/Target/SystemZ/SystemZLongBranch.cpp
lib/Target/SystemZ/SystemZRegisterInfo.cpp
lib/Target/SystemZ/SystemZRegisterInfo.h