UPSTREAM: clk: rockchip: Make uartpll a child of the gpll on rk3036
authorHeiko Stuebner <heiko@sntech.de>
Wed, 1 Mar 2017 21:00:42 +0000 (22:00 +0100)
committerHuang, Tao <huangtao@rock-chips.com>
Mon, 5 Jun 2017 08:10:51 +0000 (16:10 +0800)
commitf6e7fcae9814bc0c35ca71cd2ea31a27a33bac74
tree53ed748c7154a8f033fdd7caeb68f2b89fbfa1f8
parent9f0f403d8174f3df47c9d9d6e7094c8094765148
UPSTREAM: clk: rockchip: Make uartpll a child of the gpll on rk3036

The shared uart-pll is on boot a child of the apll that can get changed
by cpu frequency scaling. So move it away to the more stable gpll to
make sure the uart doesn't break on cpu frequency changes.

This turned up during the 4.11 merge-window when commit
6a171b299379 ("serial: 8250_dw: Allow hardware flow control to be used")
added general termios enablement making the uart on rk3036 change
frequency and thus making it susceptible for the frequency scaling issue.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from git.kernel.org mmind/linux-rockchip.git v4.13-clk/next
 commit f8ba2d68e54fbca340ad0fce97397291ba9637bc)

Change-Id: Ia8683d7b49523284043457727665d7e58d1551ec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
drivers/clk/rockchip/clk-rk3036.c