arm64: kernel: enforce pmuserenr_el0 initialization and restore
authorLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Fri, 18 Dec 2015 10:35:54 +0000 (10:35 +0000)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sun, 31 Jan 2016 19:29:04 +0000 (11:29 -0800)
commitf50c2907a9b3dfc1ba840e6cc9884cf77d9e44cc
tree8840577af68dbbe10ec4f867297faca4afc0dc5c
parent8182d4cf11a77f2c2b6afe85366e9328107b6256
arm64: kernel: enforce pmuserenr_el0 initialization and restore

commit 60792ad349f3c6dc5735aafefe5dc9121c79e320 upstream.

The pmuserenr_el0 register value is architecturally UNKNOWN on reset.
Current kernel code resets that register value iff the core pmu device is
correctly probed in the kernel. On platforms with missing DT pmu nodes (or
disabled perf events in the kernel), the pmu is not probed, therefore the
pmuserenr_el0 register is not reset in the kernel, which means that its
value retains the reset value that is architecturally UNKNOWN (system
may run with eg pmuserenr_el0 == 0x1, which means that PMU counters access
is available at EL0, which must be disallowed).

This patch adds code that resets pmuserenr_el0 on cold boot and restores
it on core resume from shutdown, so that the pmuserenr_el0 setup is
always enforced in the kernel.

Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/arm64/kernel/perf_event.c
arch/arm64/mm/proc.S