[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error...
authorDaniel Sanders <daniel.sanders@imgtec.com>
Fri, 27 Sep 2013 10:08:31 +0000 (10:08 +0000)
committerDaniel Sanders <daniel.sanders@imgtec.com>
Fri, 27 Sep 2013 10:08:31 +0000 (10:08 +0000)
commitf1ef27e6e308435035ffec112a6474ed5e009484
treee95a12e18af12ddcc5e485c2bce80ccbd3decd89
parentd2a31a124f3bebbdfc4d886afe33a116893aa689
[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
57 files changed:
lib/Target/Mips/MipsSubtarget.cpp
test/CodeGen/Mips/msa/2r.ll
test/CodeGen/Mips/msa/2r_vector_scalar.ll
test/CodeGen/Mips/msa/2rf.ll
test/CodeGen/Mips/msa/2rf_exup.ll
test/CodeGen/Mips/msa/2rf_float_int.ll
test/CodeGen/Mips/msa/2rf_fq.ll
test/CodeGen/Mips/msa/2rf_int_float.ll
test/CodeGen/Mips/msa/2rf_tq.ll
test/CodeGen/Mips/msa/3r-a.ll
test/CodeGen/Mips/msa/3r-b.ll
test/CodeGen/Mips/msa/3r-c.ll
test/CodeGen/Mips/msa/3r-d.ll
test/CodeGen/Mips/msa/3r-i.ll
test/CodeGen/Mips/msa/3r-m.ll
test/CodeGen/Mips/msa/3r-p.ll
test/CodeGen/Mips/msa/3r-s.ll
test/CodeGen/Mips/msa/3r-v.ll
test/CodeGen/Mips/msa/3r_4r.ll
test/CodeGen/Mips/msa/3r_4r_widen.ll
test/CodeGen/Mips/msa/3r_ld_st.ll
test/CodeGen/Mips/msa/3r_splat.ll
test/CodeGen/Mips/msa/3rf.ll
test/CodeGen/Mips/msa/3rf_4rf.ll
test/CodeGen/Mips/msa/3rf_4rf_q.ll
test/CodeGen/Mips/msa/3rf_exdo.ll
test/CodeGen/Mips/msa/3rf_float_int.ll
test/CodeGen/Mips/msa/3rf_int_float.ll
test/CodeGen/Mips/msa/3rf_q.ll
test/CodeGen/Mips/msa/arithmetic.ll
test/CodeGen/Mips/msa/arithmetic_float.ll
test/CodeGen/Mips/msa/basic_operations.ll
test/CodeGen/Mips/msa/basic_operations_float.ll
test/CodeGen/Mips/msa/bit.ll
test/CodeGen/Mips/msa/bitcast.ll
test/CodeGen/Mips/msa/bitwise.ll
test/CodeGen/Mips/msa/compare.ll
test/CodeGen/Mips/msa/compare_float.ll
test/CodeGen/Mips/msa/elm_copy.ll
test/CodeGen/Mips/msa/elm_cxcmsa.ll
test/CodeGen/Mips/msa/elm_insv.ll
test/CodeGen/Mips/msa/elm_move.ll
test/CodeGen/Mips/msa/elm_shift_slide.ll
test/CodeGen/Mips/msa/i10.ll
test/CodeGen/Mips/msa/i5-a.ll
test/CodeGen/Mips/msa/i5-b.ll
test/CodeGen/Mips/msa/i5-c.ll
test/CodeGen/Mips/msa/i5-m.ll
test/CodeGen/Mips/msa/i5-s.ll
test/CodeGen/Mips/msa/i5_ld_st.ll
test/CodeGen/Mips/msa/i8.ll
test/CodeGen/Mips/msa/llvm-stress-s525530439.ll
test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll
test/CodeGen/Mips/msa/shuffle.ll
test/CodeGen/Mips/msa/spill.ll
test/CodeGen/Mips/msa/vec.ll
test/CodeGen/Mips/msa/vecs10.ll