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ASoC: max98090: Correct pclk divisor settings
authorDylan Reid <dgreid@chromium.org>
Mon, 3 Nov 2014 18:28:56 +0000 (10:28 -0800)
committerMark Brown <broonie@kernel.org>
Tue, 4 Nov 2014 19:58:02 +0000 (19:58 +0000)
commitece509c10985ba93ccc8c68f808a9e767250041c
tree6d724e9e40fde130752d1f0cd1278e888a27e085tree | snapshot
parentf114040e3ea6e07372334ade75d1ee0775c355e1commit | diff
ASoC: max98090: Correct pclk divisor settings

The Baytrail-based chromebooks have a 20MHz mclk, the code was setting
the divisor incorrectly in this case.  According to the 98090
datasheet, the divisor should be set to DIV1 for 10 <= mclk <= 20.
Correct this and the surrounding clock ranges as well to match the
datasheet.

Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/codecs/max98090.c diff | blob | history
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