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(parent: 1a7ce41) | patch
update DPLL rate after change DDR frequency
authorhcy <hcy@rock-chips.com>
Fri, 28 Sep 2012 08:41:23 +0000 (16:41 +0800)
committerhcy <hcy@rock-chips.com>
Fri, 28 Sep 2012 08:41:23 +0000 (16:41 +0800)
commite8ca677ea2819455d6c52ca64893356bbd0d66c1
tree6ee056d07a5a7e8045887db5bb47f68ccba7b0dftree | snapshot
parent1a7ce41ef4428488291e5333d431bb9c0344a3a6commit | diff
update DPLL rate after change DDR frequency
arch/arm/mach-rk2928/ddr.c diff | blob | history
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