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(parent: ae85c73) | patch
ARM: teach AAPCS-VFP to deal with Cortex-M4.
authorTim Northover <tnorthover@apple.com>
Tue, 27 May 2014 10:43:38 +0000 (10:43 +0000)
committerTim Northover <tnorthover@apple.com>
Tue, 27 May 2014 10:43:38 +0000 (10:43 +0000)
commite43c5023fe0c1de8d5c1ff13d07ff710b196d121
tree9ed856584ebadab0711b006fd43537f23e3da0cdtree | snapshot
parentae85c73d4af578822bb957d94d6385d73ff57b3bcommit | diff
ARM: teach AAPCS-VFP to deal with Cortex-M4.

Cortex-M4 only has single-precision floating point support, so any LLVM
"double" type will have been split into 2 i32s by now. Fortunately, the
consecutive-register framework turns out to be precisely what's needed to
reconstruct the double and follow AAPCS-VFP correctly!

rdar://problem/17012966

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209650 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp diff | blob | history
lib/Target/ARM/ARMCallingConv.h diff | blob | history
lib/Target/ARM/ARMISelLowering.cpp diff | blob | history
test/CodeGen/ARM/aapcs-hfa-code.ll [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors