Split the ATOMIC NodeType's to include the size, e.g.
authorDale Johannesen <dalej@apple.com>
Thu, 28 Aug 2008 02:44:49 +0000 (02:44 +0000)
committerDale Johannesen <dalej@apple.com>
Thu, 28 Aug 2008 02:44:49 +0000 (02:44 +0000)
commite00a8a2a2e11a37fd1ddf2504bd22d225d0994d0
tree484cf9b89070b672dd21616a49c0f15109bd51b8
parentf2c785edf0d7ceb4491333146e289fdbbba1dddf
Split the ATOMIC NodeType's to include the size, e.g.
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55457 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/CodeGen/SelectionDAGNodes.h
include/llvm/Target/TargetLowering.h
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
lib/Target/TargetSelectionDAG.td
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86Instr64bit.td
lib/Target/X86/X86InstrInfo.td