rk29: L2 Data RAM latency set to 5 cycles, suggested by zcs
author黄涛 <huangtao@rock-chips.com>
Sat, 2 Apr 2011 09:49:14 +0000 (17:49 +0800)
committer黄涛 <huangtao@rock-chips.com>
Sat, 2 Apr 2011 09:49:28 +0000 (17:49 +0800)
commitd726549fadb3a4578d4076c54f605743a3ed0754
tree1f95f92db0d28475adbae34246b72df3dca24a2b
parente418a64850a21cc8300b5fe42b4d1ca9ce7eaeaf
rk29: L2 Data RAM latency set to 5 cycles, suggested by zcs
arch/arm/mm/proc-v7.S