ARM: mvebu: add support to clear shared L2 bit on Armada XP
authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Wed, 8 Jul 2015 14:09:20 +0000 (16:09 +0200)
committerGregory CLEMENT <gregory.clement@free-electrons.com>
Tue, 29 Sep 2015 13:31:51 +0000 (15:31 +0200)
commitd492cccac28493f26bb70038385a9ef4df19bdee
treefdbd2dbe0f112f0b32027d746915716a9608d520
parent6ff33f3902c3b1c5d0db6b1e2c70b6d76fba357f
ARM: mvebu: add support to clear shared L2 bit on Armada XP

For optimal performance, in a HW I/O coherency context such as the one
used on Armada XP, the shared L2 bit of the CPU configuration register
should be cleared.

This commit adjusts the coherency fabric code used by Marvell EBU
processors to clear this bit on Armada XP. Since it's a per-CPU
register, it's cleared in set_cpu_coherent() for the boot CPU, and
through a CPU notifier for the non-boot CPUs.

[gregory.clement@free-electrons.com: rebasd on 4.3-rc1]

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Documentation/devicetree/bindings/arm/mvebu-cpu-config.txt [new file with mode: 0644]
arch/arm/mach-mvebu/coherency.c