Correct some load / store instruction itinerary mistakes:
authorEvan Cheng <evan.cheng@apple.com>
Sat, 9 Oct 2010 01:03:04 +0000 (01:03 +0000)
committerEvan Cheng <evan.cheng@apple.com>
Sat, 9 Oct 2010 01:03:04 +0000 (01:03 +0000)
commitd2ca8135496ff7945e8a708dccb26b482e563a63
tree874a625eaa588d1d5b473c1dd1bf4a1e61407f6f
parent5ed5c38423b0211ba464cba82ef96cc8f103357e
Correct some load / store instruction itinerary mistakes:
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMInstrNEON.td
lib/Target/ARM/ARMSchedule.td
lib/Target/ARM/ARMScheduleA8.td
lib/Target/ARM/ARMScheduleA9.td
test/CodeGen/ARM/reg_sequence.ll