R600/SI: Use RegisterOperands to specify which operands can accept immediates
authorTom Stellard <thomas.stellard@amd.com>
Mon, 12 Jan 2015 19:33:18 +0000 (19:33 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Mon, 12 Jan 2015 19:33:18 +0000 (19:33 +0000)
commitd275e025d2d5468632e3b6c1c242534768d11fd0
tree54bbc3cfa8c5e7cdd02e768b5bd5820ba4c6ef44
parentb461e8304c1d1cc933e447d43fa77472bef3fe84
R600/SI: Use RegisterOperands to specify which operands can accept immediates

There are some operands which can take either immediates or registers
and we were previously using different register class to distinguish
between operands that could take immediates and those that could not.

This patch switches to using RegisterOperands which should simplify the
backend by reducing the number of register classes and also make it
easier to implement the assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225662 91177308-0d34-0410-b5e6-96231b3b80d8
15 files changed:
lib/Target/R600/AMDGPUISelDAGToDAG.cpp
lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.cpp
lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
lib/Target/R600/SIDefines.h
lib/Target/R600/SIISelLowering.cpp
lib/Target/R600/SIInstrInfo.cpp
lib/Target/R600/SIInstrInfo.td
lib/Target/R600/SIRegisterInfo.cpp
lib/Target/R600/SIRegisterInfo.h
lib/Target/R600/SIRegisterInfo.td
test/CodeGen/R600/srl.ll
test/CodeGen/R600/sub.ll
test/CodeGen/R600/udivrem.ll
test/CodeGen/R600/usubo.ll
test/CodeGen/R600/xor.ll