perf/x86/intel/pebs: Add PEBS frontend profiling for Skylake
authorAndi Kleen <ak@linux.intel.com>
Wed, 9 Sep 2015 21:53:59 +0000 (14:53 -0700)
committerIngo Molnar <mingo@kernel.org>
Fri, 18 Sep 2015 07:20:22 +0000 (09:20 +0200)
commitd0dc8494cd6904f8ad035d9ad97f313948f35d0c
tree2d75bb8c78333700c0ddba069911d6fe394475a4
parent5e176213a6b2bc5146820c79542d37290434a3c4
perf/x86/intel/pebs: Add PEBS frontend profiling for Skylake

Skylake has a new FRONTEND_LATENCY PEBS event to accurately profile
frontend problems (like ITLB or decoding issues).

The new event is configured through a separate MSR, which selects
a range of sub events.

Define the extra MSR as a extra reg and export support for it
through sysfs.  To avoid duplicating the existing
tables use a new function to add new entries to existing tables.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1435707205-6676-4-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/include/asm/msr-index.h
arch/x86/kernel/cpu/perf_event.h
arch/x86/kernel/cpu/perf_event_intel.c