x86, Calgary: Increase max PHB number
authorDarrick J. Wong <djwong@us.ibm.com>
Thu, 24 Jun 2010 21:26:47 +0000 (14:26 -0700)
committerGreg Kroah-Hartman <gregkh@suse.de>
Mon, 2 Aug 2010 17:20:51 +0000 (10:20 -0700)
commitcb5985a25d6314c90f59169c42ab15f6136d3425
treeb32cdc9b95df804e1aec29c14c6a248c4cb9728b
parent30d9fa8b70b38599667d545f49d1390cf84295c0
x86, Calgary: Increase max PHB number

commit 499a00e92dd9a75395081f595e681629eb1eebad upstream.

Newer systems (x3950M2) can have 48 PHBs per chassis and 8
chassis, so bump the limits up and provide an explanation
of the requirements for each class.

Signed-off-by: Darrick J. Wong <djwong@us.ibm.com>
Acked-by: Muli Ben-Yehuda <muli@il.ibm.com>
Cc: Corinna Schultz <cschultz@linux.vnet.ibm.com>
LKML-Reference: <20100624212647.GI15515@tux1.beaverton.ibm.com>
[ v2: Fixed build bug, added back PHBS_PER_CALGARY == 4 ]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
arch/x86/kernel/pci-calgary_64.c