powerpc: Don't try to fix up misaligned load-with-reservation instructions
authorPaul Mackerras <paulus@ozlabs.org>
Tue, 4 Apr 2017 04:56:05 +0000 (14:56 +1000)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 12 Apr 2017 10:38:34 +0000 (12:38 +0200)
commitca9bd55235b346da89dadc1821e37bb4ec22b7eb
tree63d7d9318621499249a9a676bb3f4484c70a9884
parenta67004a3896eacd109a0138b5526957381fe4337
powerpc: Don't try to fix up misaligned load-with-reservation instructions

commit 48fe9e9488743eec9b7c1addd3c93f12f2123d54 upstream.

In the past, there was only one load-with-reservation instruction,
lwarx, and if a program attempted a lwarx on a misaligned address, it
would take an alignment interrupt and the kernel handler would emulate
it as though it was lwzx, which was not really correct, but benign since
it is loading the right amount of data, and the lwarx should be paired
with a stwcx. to the same address, which would also cause an alignment
interrupt which would result in a SIGBUS being delivered to the process.

We now have 5 different sizes of load-with-reservation instruction. Of
those, lharx and ldarx cause an immediate SIGBUS by luck since their
entries in aligninfo[] overlap instructions which were not fixed up, but
lqarx overlaps with lhz and will be emulated as such. lbarx can never
generate an alignment interrupt since it only operates on 1 byte.

To straighten this out and fix the lqarx case, this adds code to detect
the l[hwdq]arx instructions and return without fixing them up, resulting
in a SIGBUS being delivered to the process.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/powerpc/kernel/align.c