[InstCombine] (mul nsw 1, INT_MIN) != (shl nsw 1, 31)
authorDavid Majnemer <david.majnemer@gmail.com>
Sat, 18 Apr 2015 04:41:30 +0000 (04:41 +0000)
committerDavid Majnemer <david.majnemer@gmail.com>
Sat, 18 Apr 2015 04:41:30 +0000 (04:41 +0000)
commitc5edbea4e74842d7c0698061c6626f297667d367
tree962be182b2e926508904f763bf03abe32e4c5856
parent35e80553937f84d1b562f00fa757ee700d142f99
[InstCombine] (mul nsw 1, INT_MIN) != (shl nsw 1, 31)

Multiplying INT_MIN by 1 doesn't trigger nsw.  However, shifting 1 into
the sign bit *does* trigger nsw.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235250 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
test/Transforms/InstCombine/mul.ll