Fixed instruction information for RDCCR and WRCCR.
authorVikram S. Adve <vadve@cs.uiuc.edu>
Sun, 4 Nov 2001 19:34:49 +0000 (19:34 +0000)
committerVikram S. Adve <vadve@cs.uiuc.edu>
Sun, 4 Nov 2001 19:34:49 +0000 (19:34 +0000)
commitb7f06f46a176b2f19349d44581b0523297c8efb9
treeb6a8073951335e67849887cc6b5a31b82ce3f826
parent8e7f4091695aad705f84398ede1fccc3796b1fad
Fixed instruction information for RDCCR and WRCCR.
Fixed selection to create a TmpInstruction for each integer CC register
(since it is an implicit side-effect, unlike FP CC registers which are
explicit operands).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1120 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/SparcV9/SparcV9Instr.def
lib/Target/SparcV9/SparcV9InstrSelection.cpp
lib/Target/SparcV9/SparcV9Internals.h