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(parent: fed90b6) | patch
Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation,
authorDan Gohman <gohman@apple.com>
Mon, 28 Jul 2008 22:18:25 +0000 (22:18 +0000)
committerDan Gohman <gohman@apple.com>
Mon, 28 Jul 2008 22:18:25 +0000 (22:18 +0000)
commitb1e8cad61e64dd7f56b0c62b53f9c1fc86d599f7
treefaaed90dd3b7d23f7a990f7846bb2d79263ec383tree | snapshot
parentfed90b6d097d50881afb45e4d79f430db66dd741commit | diff
Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation,
which is represented in codegen as an 'and' operation. This matches them
with movz instructions, instead of leaving them to be matched by and
instructions with an immediate field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54147 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/CodeGen/SelectionDAGNodes.h diff | blob | history
lib/Target/X86/X86Instr64bit.td diff | blob | history
lib/Target/X86/X86InstrInfo.td diff | blob | history
test/CodeGen/X86/zext-inreg-0.ll [new file with mode: 0644] blob
test/CodeGen/X86/zext-inreg-1.ll [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors