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clk: rockchip: rk3399: fix PPLL is redefined and ID shouldn't be 0
authorXing Zheng <zhengxing@rock-chips.com>
Thu, 24 Mar 2016 08:01:36 +0000 (16:01 +0800)
committerGerrit Code Review <gerrit@rock-chips.com>
Thu, 24 Mar 2016 08:39:29 +0000 (16:39 +0800)
commitac75497ee3371c50ef9c064ec9d626717af780dd
treea8e7c7de12e0f7c9bc6ed49752fb62afae723fa0tree | snapshot
parent2ef6df639e07b312f9cde351ba4a5d28c0009a82commit | diff
clk: rockchip: rk3399: fix PPLL is redefined and ID shouldn't be 0

PPLL is 8 and redefined by SCLK_I2C4_PMU, and clock IDs shouldn't be 0.

Change-Id: I50f89487034c1f1ef41d257de00b7f3ec53f7f4c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
include/dt-bindings/clock/rk3399-cru.h diff | blob | history
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