Loosen scheduling restrictions on the PPC dcbt intrinsic
authorHal Finkel <hfinkel@anl.gov>
Tue, 25 Dec 2012 18:51:18 +0000 (18:51 +0000)
committerHal Finkel <hfinkel@anl.gov>
Tue, 25 Dec 2012 18:51:18 +0000 (18:51 +0000)
commitabdf75511be5d0b4239157a5fd86c3c84e10e5bf
tree084d45812779a31213b82d098c140bee7fbfda08
parentcd9ea5198660a80c9c28c6471b0983bb450ca8cb
Loosen scheduling restrictions on the PPC dcbt intrinsic

As with the prefetch intrinsic to which it maps, simply have dcbt
marked as reading from and writing to its arguments instead of having
unmodeled side effects. While this might cause unwanted code motion
(because aliasing checks don't really capture cache-line sharing),
it is more important that prefetches in unrolled loops don't block
the scheduler from rearranging the unrolled loop body.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171073 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/IntrinsicsPowerPC.td
test/CodeGen/PowerPC/dcbt-sched.ll [new file with mode: 0644]