Narrow right shifts need to encode their immediates differently from a normal
authorBill Wendling <isanbard@gmail.com>
Tue, 1 Mar 2011 01:00:59 +0000 (01:00 +0000)
committerBill Wendling <isanbard@gmail.com>
Tue, 1 Mar 2011 01:00:59 +0000 (01:00 +0000)
commita656b63ee4d5b0e3f4d26a55dd4cc69795746684
tree207aa0386e59701c56483a84bcc30708bb82795d
parentf291ab2fbaa5ed1cfa20ca47e8dece1040a5065b
Narrow right shifts need to encode their immediates differently from a normal
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMCodeEmitter.cpp
lib/Target/ARM/ARMInstrFormats.td
lib/Target/ARM/ARMInstrNEON.td
lib/Target/ARM/ARMMCCodeEmitter.cpp
test/CodeGen/ARM/neon_shift.ll [new file with mode: 0644]
test/MC/ARM/neon-shift-encoding.s
utils/TableGen/EDEmitter.cpp