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(parent: 50fa2ff) | patch
R600/SI: Move SIFixSGPRCopies to inst selector passes
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 18 Nov 2014 21:06:58 +0000 (21:06 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 18 Nov 2014 21:06:58 +0000 (21:06 +0000)
commita1404487802c2dcf2b8ca0e187aa46247d96595f
tree656e50619f170ea270aacb8cf3f6b49974c226f9tree | snapshot
parent50fa2ff5d278fc012ba2942c4c98d678a2ee6348commit | diff
R600/SI: Move SIFixSGPRCopies to inst selector passes

This should expose more of the actually used VALU
instructions to the machine optimization passes.

This also should help getting i1 handling into a better state.
For not entirly understood reasons, this fixes the split-scalar-i64-add.ll
test where a 64-bit add would only partially be moved to the VALU
resulting in use of undefined VCC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222256 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/R600/AMDGPUTargetMachine.cpp diff | blob | history
test/CodeGen/R600/i1-copy-implicit-def.ll diff | blob | history
test/CodeGen/R600/i1-copy-phi.ll diff | blob | history
test/CodeGen/R600/split-scalar-i64-add.ll diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors