Merge consecutive 16-byte loads into one 32-byte load (PR22329)
authorSanjay Patel <spatel@rotateright.com>
Tue, 3 Feb 2015 18:54:00 +0000 (18:54 +0000)
committerSanjay Patel <spatel@rotateright.com>
Tue, 3 Feb 2015 18:54:00 +0000 (18:54 +0000)
commit9b4cc76745cff2f823e726981febd83a8b6e05b3
tree5d77d767a81ee333ea44d9357406f6573c29e2fb
parent93e763c5cbc387995ba47448cb3a9df39c11649e
Merge consecutive 16-byte loads into one 32-byte load (PR22329)

This patch detects consecutive vector loads using the existing
EltsFromConsecutiveLoads() logic. This fixes:
http://llvm.org/bugs/show_bug.cgi?id=22329

This patch effectively reverts the tablegen additions of D6492 /
http://reviews.llvm.org/rL224344 ...which in hindsight were a horrible hack.

The test cases that were added with that patch are simply modified to load
from varying offsets of a base pointer. These loads did not match the existing
tablegen patterns.

A happy side effect of doing this optimization earlier is that we can now fold
the load into a math op where possible; this is shown in some of the updated
checks in the test file.

Differential Revision: http://reviews.llvm.org/D7303

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228006 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86InstrSSE.td
test/CodeGen/X86/unaligned-32-byte-memops.ll