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OMAP3: PM: Clear the SCTLR C bit in asm code to prevent data cache allocation
authorSantosh Shilimkar <santosh.shilimkar@ti.com>
Sun, 23 Jan 2011 17:21:09 +0000 (22:51 +0530)
committerKevin Hilman <khilman@ti.com>
Thu, 10 Mar 2011 20:23:13 +0000 (12:23 -0800)
commit9062511097683b4422f023d181b4a8b2db1a7a72
tree9e46fb8c0491a26bb25464d90b6cd4caf92edf5btree | snapshot
parent46f557cb453b9f3b6dc36b8179c2c36932a2ea64commit | diff
OMAP3: PM: Clear the SCTLR C bit in asm code to prevent data cache allocation

On the newer ARM processors like CortexA8, CortexA9, the caches can be
speculatively loaded while they are getting flushed.

Clear the SCTLR C bit to prevent further data cache allocation as
part of cache clean routine

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
arch/arm/mach-omap2/sleep34xx.S diff | blob | history
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