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(parent: 28e9901) | patch
clk: rockchip: set aclk_core_div to 4 for all rates in rk3036_apll_table
authordkl <dkl@rock-chips.com>
Wed, 17 Dec 2014 08:36:17 +0000 (16:36 +0800)
committerdkl <dkl@rock-chips.com>
Fri, 26 Dec 2014 02:11:39 +0000 (10:11 +0800)
commit72dca47db44009a46ade2691ecc853c3600449f9
tree5cbaf58672b9dfe0351ba0347fdc22126c94c7adtree | snapshot
parent28e9901cf058f17092b91347c0df0bad62962e5ecommit | diff
clk: rockchip: set aclk_core_div to 4 for all rates in rk3036_apll_table

Set aclk_core_div to 4 for all rates, which makes rk3126\rk3128\rk3126b apll
frequency change stably.

Signed-off-by: dkl <dkl@rock-chips.com>
drivers/clk/rockchip/clk-pll.c diff | blob | history
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