[ARM64] Ports the Cortex-A53 Machine Model description from AArch64.
authorChad Rosier <mcrosier@codeaurora.org>
Fri, 18 Apr 2014 21:22:04 +0000 (21:22 +0000)
committerChad Rosier <mcrosier@codeaurora.org>
Fri, 18 Apr 2014 21:22:04 +0000 (21:22 +0000)
commit6c4ec69c6be8b0003b420b58df585caa0563ef70
tree218f64492fbff02fa2c8fea3f34940f01f2dc069
parented5604850a0dbb79dd41a8d950b776e553992fa3
[ARM64] Ports the Cortex-A53 Machine Model description from AArch64.

Summary:
This port includes the rudimentary latencies that were provided for
the Cortex-A53 Machine Model in the AArch64 backend. It also changes
the SchedAlias for COPY in the Cyclone model to an explicit
WriteRes mapping to avoid conflicts in other subtargets.

Differential Revision: http://reviews.llvm.org/D3427
Patch by Dave Estes <cestes@codeaurora.org>!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206652 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM64/ARM64.td
lib/Target/ARM64/ARM64SchedA53.td [new file with mode: 0644]
lib/Target/ARM64/ARM64SchedCyclone.td
test/CodeGen/ARM64/misched-basic-A53.ll [new file with mode: 0644]