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drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2
authorChon Ming Lee <chon.ming.lee@intel.com>
Tue, 3 Sep 2013 17:30:38 +0000 (01:30 +0800)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 4 Sep 2013 15:34:58 +0000 (17:34 +0200)
commit65ce4bf5a15fcd4d15898be47795d0550eb2325c
tree3b2ce08e8e1c034921ef83dc401d0876fb13cce0tree | snapshot
parent9dd4ffdf3936e9cd85a5c856a192134b23b4b2accommit | diff
drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2

For DP pll settings, there is only two golden configs.  Instead of
running through the algorithm to determine it, hardcode the value and get it
determine in intel_dp_set_clock.

v2: Rework on the intel_limit compiler warning. (Jani)

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
[danvet: Fix up checkpatch issues.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c diff | blob | history
drivers/gpu/drm/i915/intel_dp.c diff | blob | history
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