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(parent: 023a6e3) | patch
AArch64: Fix loads to lower NEON vector lanes using GPR registers
authorMatthias Braun <matze@braunis.de>
Mon, 31 Aug 2015 18:25:15 +0000 (18:25 +0000)
committerMatthias Braun <matze@braunis.de>
Mon, 31 Aug 2015 18:25:15 +0000 (18:25 +0000)
commit5c084f66bc8bf3100ecf534d8bf597048ec8395c
treee3873e9948e3e7a3071588a385c7dc4041edc5f3tree | snapshot
parent023a6e3548c7e1890a1a9b3ddda969e85fe6f0d2commit | diff
AArch64: Fix loads to lower NEON vector lanes using GPR registers

The ISelLowering code turned insertion turned the element for the
lowest lane of a BUILD_VECTOR into an INSERT_SUBREG, this prohibited
the patterns for SCALAR_TO_VECTOR(Load) to match later. Restrict this
to cases without a load argument.

Reported in rdar://22223823

Differential Revision: http://reviews.llvm.org/D12467

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246462 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors