projects / oota-llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 8da7a46) | patch
The ARM instructions that have an unpredictable behavior when the pc register operand...
authorSilviu Baranga <silviu.baranga@arm.com>
Tue, 20 Mar 2012 15:54:56 +0000 (15:54 +0000)
committerSilviu Baranga <silviu.baranga@arm.com>
Tue, 20 Mar 2012 15:54:56 +0000 (15:54 +0000)
commit5c062ad92672f22e61a4b20a9954af3db3b72bd6
treef65d4278663391396a3ae5ab55a3a4b7021200edtree | snapshot
parent8da7a4668f6f32e565d426b5cca93eea9278f482commit | diff
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
12 files changed:
lib/Target/ARM/ARMInstrInfo.td diff | blob | history
lib/Target/ARM/Disassembler/ARMDisassembler.cpp diff | blob | history
test/MC/Disassembler/ARM/invalid-LSL-regform.txt [deleted file] blob | history
test/MC/Disassembler/ARM/invalid-RSC-arm.txt [deleted file] blob | history
test/MC/Disassembler/ARM/invalid-SSAT-arm.txt [deleted file] blob | history
test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt [deleted file] blob | history
test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt [deleted file] blob | history
test/MC/Disassembler/ARM/unpredictable-LSL-regform.txt [new file with mode: 0644] blob
test/MC/Disassembler/ARM/unpredictable-RSC-arm.txt [new file with mode: 0644] blob
test/MC/Disassembler/ARM/unpredictable-SSAT-arm.txt [new file with mode: 0644] blob
test/MC/Disassembler/ARM/unpredictable-STRBrs-arm.txt [new file with mode: 0644] blob
test/MC/Disassembler/ARM/unpredictable-UQADD8-arm.txt [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors