drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link
authorGaurav K Singh <gaurav.k.singh@intel.com>
Thu, 4 Dec 2014 05:28:52 +0000 (10:58 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 5 Dec 2014 14:28:45 +0000 (15:28 +0100)
commit58cf8887c94d8dfe42206af7de57163ce0f46cf2
tree6563ca1834857d0b292b2ff2d681fc69b5984620
parent4510cd779e5897eeb8691aecbd639bb62ec27d55
drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link

For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.

v2: Address review comments by Jani
    - Added wait time for PLL to be locked.

v3: separate patch created for cck read for checking PLL to be locked

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_dsi_pll.c