Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because...
authorCraig Topper <craig.topper@gmail.com>
Sat, 15 Oct 2011 20:46:47 +0000 (20:46 +0000)
committerCraig Topper <craig.topper@gmail.com>
Sat, 15 Oct 2011 20:46:47 +0000 (20:46 +0000)
commit566f233ba64c0bb2773b5717cb18753c7564f4b7
treebefeba913e8cabb5cdec9d4aa59a6b9700178645
parent4d83b79c76044e3f3cefd2a6c1b0b792266935c8
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/MCTargetDesc/X86BaseInfo.h
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
lib/Target/X86/X86InstrInfo.td
test/MC/Disassembler/X86/simple-tests.txt
test/MC/Disassembler/X86/x86-32.txt
test/MC/X86/x86_64-bmi-encoding.s [new file with mode: 0644]
utils/TableGen/X86RecognizableInstr.cpp